Hi Maciej,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on v4.14 next-20171116]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:    
https://github.com/0day-ci/linux/commits/Maciej-Purski/drm-bridge-sii8620-add-DVI-mode-support/20171110-113120
base:   git://people.freedesktop.org/~airlied/linux.git drm-next

New smatch warnings:
drivers/gpu/drm/bridge/sil-sii8620.c:1218 sii8620_start_video() error: buffer 
overflow 'clk_spec' 3 <= 3

Old smatch warnings:
drivers/gpu/drm/bridge/sil-sii8620.c:1223 sii8620_start_video() error: buffer 
overflow 'clk_spec' 3 <= 3
drivers/gpu/drm/bridge/sil-sii8620.c:1230 sii8620_start_video() error: buffer 
overflow 'clk_spec' 3 <= 3
drivers/gpu/drm/bridge/sil-sii8620.c:1237 sii8620_start_video() error: buffer 
overflow 'clk_spec' 3 <= 3

# 
https://github.com/0day-ci/linux/commit/cbac7504ac0eccdd1c2ac8597359bbf1b3615c4e
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout cbac7504ac0eccdd1c2ac8597359bbf1b3615c4e
vim +/clk_spec +1218 drivers/gpu/drm/bridge/sil-sii8620.c

bf1722ca Andrzej Hajda 2017-02-01  1171  
cbac7504 Maciej Purski 2017-11-09  1172  static void sii8620_start_video(struct 
sii8620 *ctx)
ce6e153f Andrzej Hajda 2016-10-10  1173  {
cbac7504 Maciej Purski 2017-11-09  1174         if (!sii8620_is_mhl3(ctx))
cbac7504 Maciej Purski 2017-11-09  1175                 sii8620_stop_video(ctx);
cbac7504 Maciej Purski 2017-11-09  1176  
cbac7504 Maciej Purski 2017-11-09  1177         if (ctx->sink_type == SINK_DVI 
&& !sii8620_is_mhl3(ctx)) {
cbac7504 Maciej Purski 2017-11-09  1178                 sii8620_write(ctx, 
REG_RX_HDMI_CTRL2,
cbac7504 Maciej Purski 2017-11-09  1179                               
VAL_RX_HDMI_CTRL2_DEFVAL_DVI);
cbac7504 Maciej Purski 2017-11-09  1180                 sii8620_write(ctx, 
REG_TPI_SC,
cbac7504 Maciej Purski 2017-11-09  1181                               
BIT_TPI_SC_TPI_OUTPUT_MODE_0_DVI);
cbac7504 Maciej Purski 2017-11-09  1182                 return;
cbac7504 Maciej Purski 2017-11-09  1183         }
cbac7504 Maciej Purski 2017-11-09  1184  
ce6e153f Andrzej Hajda 2016-10-10  1185         sii8620_write_seq_static(ctx,
ce6e153f Andrzej Hajda 2016-10-10  1186                 REG_RX_HDMI_CTRL2, 
VAL_RX_HDMI_CTRL2_DEFVAL
ce6e153f Andrzej Hajda 2016-10-10  1187                         | 
BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
ce6e153f Andrzej Hajda 2016-10-10  1188                 REG_VID_OVRRD, 
BIT_VID_OVRRD_PP_AUTO_DISABLE
bf1722ca Andrzej Hajda 2017-02-01  1189                         | 
BIT_VID_OVRRD_M1080P_OVRRD);
bf1722ca Andrzej Hajda 2017-02-01  1190         sii8620_set_format(ctx);
ce6e153f Andrzej Hajda 2016-10-10  1191  
bf1722ca Andrzej Hajda 2017-02-01  1192         if (!sii8620_is_mhl3(ctx)) {
ce6e153f Andrzej Hajda 2016-10-10  1193                 
sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
bf1722ca Andrzej Hajda 2017-02-01  1194                         
MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED);
ce6e153f Andrzej Hajda 2016-10-10  1195                 
sii8620_set_auto_zone(ctx);
bf1722ca Andrzej Hajda 2017-02-01  1196         } else {
bf1722ca Andrzej Hajda 2017-02-01  1197                 static const struct {
bf1722ca Andrzej Hajda 2017-02-01  1198                         int max_clk;
bf1722ca Andrzej Hajda 2017-02-01  1199                         u8 zone;
bf1722ca Andrzej Hajda 2017-02-01  1200                         u8 link_rate;
bf1722ca Andrzej Hajda 2017-02-01  1201                         u8 rrp_decode;
bf1722ca Andrzej Hajda 2017-02-01  1202                 } clk_spec[] = {
bf1722ca Andrzej Hajda 2017-02-01  1203                         { 150000, 
VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
bf1722ca Andrzej Hajda 2017-02-01  1204                           
MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
bf1722ca Andrzej Hajda 2017-02-01  1205                         { 300000, 
VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
bf1722ca Andrzej Hajda 2017-02-01  1206                           
MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
bf1722ca Andrzej Hajda 2017-02-01  1207                         { 600000, 
VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
bf1722ca Andrzej Hajda 2017-02-01  1208                           
MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
bf1722ca Andrzej Hajda 2017-02-01  1209                 };
bf1722ca Andrzej Hajda 2017-02-01  1210                 u8 p0_ctrl = 
BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
bf1722ca Andrzej Hajda 2017-02-01  1211                 int clk = 
ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3);
bf1722ca Andrzej Hajda 2017-02-01  1212                 int i;
ce6e153f Andrzej Hajda 2016-10-10  1213  
bf1722ca Andrzej Hajda 2017-02-01  1214                 for (i = 0; i < 
ARRAY_SIZE(clk_spec); ++i)
bf1722ca Andrzej Hajda 2017-02-01  1215                         if (clk < 
clk_spec[i].max_clk)
bf1722ca Andrzej Hajda 2017-02-01  1216                                 break;
ce6e153f Andrzej Hajda 2016-10-10  1217  
bf1722ca Andrzej Hajda 2017-02-01 @1218                 if (100 * clk >= 98 * 
clk_spec[i].max_clk)
bf1722ca Andrzej Hajda 2017-02-01  1219                         p0_ctrl |= 
BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
bf1722ca Andrzej Hajda 2017-02-01  1220  
bf1722ca Andrzej Hajda 2017-02-01  1221                 
sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
bf1722ca Andrzej Hajda 2017-02-01  1222                 sii8620_burst_send(ctx);
bf1722ca Andrzej Hajda 2017-02-01  1223                 sii8620_write_seq(ctx,
bf1722ca Andrzej Hajda 2017-02-01  1224                         
REG_MHL_DP_CTL0, 0xf0,
bf1722ca Andrzej Hajda 2017-02-01  1225                         
REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
bf1722ca Andrzej Hajda 2017-02-01  1226                 sii8620_setbits(ctx, 
REG_M3_P0CTRL,
bf1722ca Andrzej Hajda 2017-02-01  1227                         
BIT_M3_P0CTRL_MHL3_P0_PORT_EN
bf1722ca Andrzej Hajda 2017-02-01  1228                         | 
BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
bf1722ca Andrzej Hajda 2017-02-01  1229                 sii8620_setbits(ctx, 
REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
bf1722ca Andrzej Hajda 2017-02-01  1230                         
clk_spec[i].rrp_decode);
bf1722ca Andrzej Hajda 2017-02-01  1231                 
sii8620_write_seq_static(ctx,
bf1722ca Andrzej Hajda 2017-02-01  1232                         REG_M3_CTRL, 
VAL_M3_CTRL_MHL3_VALUE
bf1722ca Andrzej Hajda 2017-02-01  1233                                 | 
BIT_M3_CTRL_H2M_SWRST,
bf1722ca Andrzej Hajda 2017-02-01  1234                         REG_M3_CTRL, 
VAL_M3_CTRL_MHL3_VALUE
bf1722ca Andrzej Hajda 2017-02-01  1235                 );
bf1722ca Andrzej Hajda 2017-02-01  1236                 
sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
bf1722ca Andrzej Hajda 2017-02-01  1237                         
clk_spec[i].link_rate);
bf1722ca Andrzej Hajda 2017-02-01  1238         }
ce6e153f Andrzej Hajda 2016-10-10  1239  
bf1722ca Andrzej Hajda 2017-02-01  1240         sii8620_set_infoframes(ctx);
ce6e153f Andrzej Hajda 2016-10-10  1241  }
ce6e153f Andrzej Hajda 2016-10-10  1242  

---
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