@kernelnewbies.org
Subject: RE: How to measure the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From: coolsandyfor...@gmail.com
Date: Tue, 26 Feb 2013 17:01:54 +0530
Subject: How to measure
:
From: bu...@live.cn
To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org
Subject: RE: How to measure the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From
:
From: bu...@live.cn
To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org
Subject: RE: How to measure the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From: coolsandyfor...@gmail.com
On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi ankurengg2...@gmail.com wrote:
I am not sure but what if you make the variable as a volatile?
Volatile in simple terms
==
Consider this eg:
1 int main(void){
2 int a, x, y;
3 x=a;
4 y=a;
5 }
Line 3 with be converted to a LDR
I am not sure but what if you make the variable as a volatile?
Hey i tried. But still is showing the same time for int volatile int.
Thanks
Sandeep
On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi ankurengg2...@gmail.comwrote:
I am not sure but what if you make the variable as a volatile?
let' see
what if you do read and write pattern, in certain order so that it
will be invalidated by the L1/L2/L3 cache everytime?
And how do you suggest we do that?? That is infact my question..
On Tue, Feb 26, 2013 at 9:05 PM, Mulyadi Santosa
mulyadi.sant...@gmail.comwrote:
On Tue, Feb
volatile only say to the compiler to not put the variable in a register.
Could i ask why does you want to mesure the speed of the RAM ? Is it to
study the NUMA behavior of the machine?
In development phase of the board, we are trying to measure RAM performance
gain while changing type of the RAM.
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar
coolsandyfor...@gmail.com wrote:
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my DDR(RAM chip) performance.
So i want to make sure, every read/write
On Wed, Feb 27, 2013 at 6:16 PM, sandeep kumar
coolsandyfor...@gmail.com wrote:
Try below points:
1. I am not sure about snapdragon(is it Qualcomm?) but try
CONFIG_CPU_DCACHE_DISABLE.
I did that already, device is not booting. In our architecture cache is
tightly coupled with CPU.
Should be
From: coolsandyfor...@gmail.com
Date: Tue, 26 Feb 2013 17:01:54 +0530
Subject: How to measure the RAM read/write performance
To: kernelnewbies@kernelnewbies.org
CC: dhyla...@gmail.com
Hi All
In performance benchmark tools, When we profile read/write
From: bu...@live.cn
To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org
Subject: RE: How to measure the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From
On Wed, 27 Feb 2013 15:38:00 +0530, sandeep kumar said:
In development phase of the board, we are trying to measure RAM performance
gain while changing type of the RAM.
The standard benchmark tools are giving us the Cache performance only. So
we want to try some method to measure RAM
the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From: coolsandyfor...@gmail.com
Date: Tue, 26 Feb 2013 17:01:54 +0530
Subject: How to measure the RAM read/write performance
To: kernelnewbies
To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org
Subject: RE: How to measure the RAM read/write performance
Date: Wed, 27 Feb 2013 22:33:15 +0800
CC: dhyla...@gmail.com
From: coolsandyfor...@gmail.com
Date: Tue, 26 Feb 2013 17:01:54 +0530
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my DDR(RAM chip) performance.
So i want to make sure, every read/write should happen to DDR RAM chip only.
How can i achieve this...Any
The mechanism to disable the L1/L2 memory caches of the CPU will depend on
the processor architecture itself. This can be possibly be done at kernel
boot-time or more preferably, in your case, through a kernel module.
For Intel x86, the kernel module would look something like following: (The
key
I am not sure but what if you make the variable as a volatile?
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.comwrote:
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my
On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumar
coolsandyfor...@gmail.com wrote:
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my DDR(RAM chip) performance.
So i want to make sure, every read/write
On Tue, 26 Feb 2013 22:35:35 +0700, Mulyadi Santosa said:
let' see
what if you do read and write pattern, in certain order so that it
will be invalidated by the L1/L2/L3 cache everytime?
AFAIK, one thing for sure, reading data from sequentially and re-read
them will make end up reading
On Tue, Feb 26, 2013 at 11:57 PM, valdis.kletni...@vt.edu wrote:
Of you could just download a copy of memtest+ and run that - I think that
provides some timing info in addition to actually testing your memory.
How could I missed memtest ! :) Of course, that's the easiest way I
could think
How could I missed memtest ! :) Of course, that's the easiest way I
could think of... if the OP doesn't mind with non programming method
IMHO
But i want to check it on ARM based Android board..
On Wed, Feb 27, 2013 at 6:12 AM, Mulyadi Santosa
mulyadi.sant...@gmail.comwrote:
On Tue, Feb 26,
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