On Fri, Jul 7, 2017 at 9:39 AM, Tom Lendacky wrote:
> Currently there is a check if the address being mapped is in the ISA
> range (is_ISA_range()), and if it is, then phys_to_virt() is used to
> perform the mapping. When SME is active, the default is to add pagetable
>
On Fri, Jul 7, 2017 at 9:38 AM, Tom Lendacky wrote:
> Update the CPU features to include identifying and reporting on the
> Secure Memory Encryption (SME) feature. SME is identified by CPUID
> 0x801f, but requires BIOS support to enable it (set bit 23 of
>
* Tom Lendacky wrote:
> This patch series provides support for AMD's new Secure Memory Encryption
> (SME)
> feature.
I'm wondering, what's the typical performance hit to DRAM access latency when
SME
is enabled?
On that same note, if the performance hit is