On Wed, Apr 24, 2024 at 1:53 PM Ard Biesheuvel wrote:
>
> Hi Brian,
>
> Thanks for taking a look.
>
> On Wed, 24 Apr 2024 at 19:39, Brian Gerst wrote:
> >
> > On Wed, Apr 24, 2024 at 12:06 PM Ard Biesheuvel wrote:
> > >
> > > From: Ard Biesheuv
SYM_DATA_START_LOCAL(gdt)
> * 0x08 unused
> * so use them as gdt ptr
obsolete comment
> */
> - .word gdt_end - gdt - 1
> - .quad gdt
> + .word 0
> + .quad 0
> .word 0, 0, 0
This can be condensed down to:
.quad 0, 0
>
>
An alternative to the patch I proposed earlier would be to use aliases
with the __x32_ prefix for the common syscalls.
--
Brian Gerst
On Sat, Sep 19, 2020 at 1:14 PM wrote:
>
> On September 19, 2020 9:23:22 AM PDT, Andy Lutomirski wrote:
> >On Fri, Sep 18, 2020 at 10:35 PM Chris
On Tue, Jul 11, 2017 at 11:02 AM, Tom Lendacky <thomas.lenda...@amd.com> wrote:
> On 7/10/2017 11:58 PM, Brian Gerst wrote:
>>
>> On Mon, Jul 10, 2017 at 3:50 PM, Tom Lendacky <thomas.lenda...@amd.com>
>> wrote:
>>>
>>> On 7/8/2017 7:57 AM, Br
On Tue, Jul 11, 2017 at 4:35 AM, Arnd Bergmann <a...@arndb.de> wrote:
> On Tue, Jul 11, 2017 at 6:58 AM, Brian Gerst <brge...@gmail.com> wrote:
>> On Mon, Jul 10, 2017 at 3:50 PM, Tom Lendacky <thomas.lenda...@amd.com>
>> wrote:
>>> On 7/8/2017 7:57 AM, B
On Mon, Jul 10, 2017 at 3:41 PM, Tom Lendacky <thomas.lenda...@amd.com> wrote:
> On 7/8/2017 7:50 AM, Brian Gerst wrote:
>>
>> On Fri, Jul 7, 2017 at 9:38 AM, Tom Lendacky <thomas.lenda...@amd.com>
>> wrote:
>>>
>>> Update the CPU features to
On Mon, Jul 10, 2017 at 3:50 PM, Tom Lendacky <thomas.lenda...@amd.com> wrote:
> On 7/8/2017 7:57 AM, Brian Gerst wrote:
>>
>> On Fri, Jul 7, 2017 at 9:39 AM, Tom Lendacky <thomas.lenda...@amd.com>
>> wrote:
>>>
>>> Currently there is a check
..
> */
> pfn = phys_addr >> PAGE_SHIFT;
>
Removing this also affects 32-bit, which is more likely to access
legacy devices in this range. Put in a check for SME instead
(provided you follow my recommendations to not set the SME feature bit
on 32-bit
struct cpuid_bit {
> { X86_FEATURE_HW_PSTATE,CPUID_EDX, 7, 0x8007, 0 },
> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x8007, 0 },
> { X86_FEATURE_PROC_FEEDBACK,CPUID_EDX, 11, 0x8007, 0 },
> + { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000
