I managed to do this successfully a few weeks back with boost-1.69.0. Now
with boost-1.70.0 it fails.
The relevant parts of my (SlackBuilds based) build script are,
SLKCFLAGS="-O2 -fPIC"
LIBDIRSUFFIX="64"
cmake \
-DCMAKE_C_FLAGS:STRING="$SLKCFLAGS" \
On 24/04/2019 13:38, John Beard wrote:
I have here a couple of patches that enable unit tests in eeschema's
library code.
this is a proposal to merge the changes attached, at the cost of
another heavy link. However, having a working eeschema test suite will
allow such things as eeschema's
OK, so the config statement is in the dev docs, but I’m not sure it should be.
Now that 4.x is a few versions behind us, I think we should retire all the doc
about building without kicad-mac-builder. Does that sound reasonable?
Either way, we need to update the config of kicad-mac-builder.
It should work now, and it may also be a bit more responsive.
On Thu, 9 May 2019 at 16:16, Nick Østergaard wrote:
>
> I know. I will report back when it works.
>
> tor. 9. maj 2019 16.15 skrev Jon Evans :
>>
>> Still down
>>
>> On Wed, May 8, 2019 at 3:27 PM Wayne Stambaugh wrote:
>>>
>>> Still
Hi Henner,
On 5/1/19 9:44 AM, Henner Zeller wrote:
> On Wed, 1 May 2019 at 06:14, John Beard wrote:
>>
>> On 01/05/2019 13:57, Mário Luzeiro wrote:
>>> Hi John,
>>>
>>> yeah the Morton code is to improve cache hits.
>>>
>>> Regarding the speed test, since OS are multi-tasking there could be some
Hi,
Just a thought. This feature could also be very useful to import/export of FPGA
physical constrain files (PCF). This would allow us to keep the pin naming in
sync between the schematic and HDL. Maybe even simplify pin swapping?
Cheers,
Piotr
> On May 9, 2019, at 7:55 AM, Johannes Wågen
I don’t know whether the configure statement is in them or not. (I haven’t
been able to check because it seems the server is down.)
New folks won’t need the rest of the instructions as they’ll be building from
scratch.
Cheers,
Jeff.
> On 9 May 2019, at 17:28, Michael Kavanagh wrote:
>
>
Should the build instructions in the developers docs be updated?
Cheers,
Michael
On Thu, 9 May 2019 at 00:03, Jeff Young wrote:
> I’ve added a check in the headers that will *fail* a compile if
> wxUSE_UNICODE_UTF8 is set. This will allow us to remove a bunch of our
> mutex hacks. (It turns
Hi,
In today's version I experience a segfault anytime a paste operation is
aborted using the "esc" key.
How to reproduce the behaviour.
-Create a new schematic
-Add a GND symbol
-Copy it with ctrl-c
-Paste it with ctrl-v, without confirming with click or enter
-ESC key to abort,
then an
...I forgot to paste version information... here they are
--
Application: kicad
Version: (5.1.0-512-g5f4a6e33a), debug build
Libraries:
wxWidgets 3.0.2
libcurl/7.52.1 OpenSSL/1.0.2r zlib/1.2.8 libidn2/0.16 libpsl/0.17.0
(+libidn2/0.16) libssh2/1.7.0
Hi
The open source FPGA tools also have this. It might be worth to take a
look at[1]. It is written in JavaScript, but it does perhaps give some
indication of what such a tool could be capable of.
[1] https://github.com/nturley/netlistsvg
-Johannes Wågen
Den 09.05.2019 14:32, skrev Reece
I know. I will report back when it works.
tor. 9. maj 2019 16.15 skrev Jon Evans :
> Still down
>
> On Wed, May 8, 2019 at 3:27 PM Wayne Stambaugh
> wrote:
>
>> Still no luck :(
>>
>> On 5/8/19 10:12 AM, Nick Østergaard wrote:
>> > Ok, thank you for the notification.
>> >
>> > It looks like the
Still down
On Wed, May 8, 2019 at 3:27 PM Wayne Stambaugh wrote:
> Still no luck :(
>
> On 5/8/19 10:12 AM, Nick Østergaard wrote:
> > Ok, thank you for the notification.
> >
> > It looks like the publish job jot stuck in a retry loop, I have
> > restarted it and it should be back within half
You might want to take a look at how Xilinx ISE and similar products handle
this. Their tools take in Verilog or VHDL and can produce a graphical
representation of the resulting logic. It's not as readable as a hand-drawn
schematic but it exists and enough people find it useful that Xilinx
Sorry about that, here's the patch
From e7586acb334955de22786d76e28f5374d2446d2c Mon Sep 17 00:00:00 2001
From: Mark
Date: Thu, 9 May 2019 09:53:46 +0200
Subject: [PATCH] Fix for SWIG 4.0.0
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="2.21.0"
This is a multi-part
Nothing attached
tor. 9. maj 2019 09.45 skrev :
>
>
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Hi Russell,
On 5/4/19 12:38 AM, Russell Oliver wrote:
> 2. Thinking about it further the task of generating a graphical
> schematic shouldn't be too difficult using the SKIDL library. I
> suspect Dave would be disappointed in me for being addicted to
> schematics. A simple grid based layout with
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