On 01.05.2017 08:39, jp charras wrote:
>> Hi,
>>
>> Lachlan sent me a complex board in Eagle that has several copper zones,
>> each with different clearances, which filled incorrectly or didn't fill
>> at all. There were some trivial issues (e.g. inverted filling priority),
>> but there is one that
Le 01/05/2017 à 10:37, Nick Østergaard a écrit :
> 2017-05-01 8:25 GMT+02:00 jp charras :
>>> Hi,
>>>
>>> Lachlan sent me a complex board in Eagle that has several copper zones,
>>> each with different clearances, which filled incorrectly or didn't fill
>>> at all. There were some trivial issues (e
2017-05-01 8:25 GMT+02:00 jp charras :
>> Hi,
>>
>> Lachlan sent me a complex board in Eagle that has several copper zones,
>> each with different clearances, which filled incorrectly or didn't fill
>> at all. There were some trivial issues (e.g. inverted filling priority),
>> but there is one that
> Hi,
>
> Lachlan sent me a complex board in Eagle that has several copper zones,
> each with different clearances, which filled incorrectly or didn't fill
> at all. There were some trivial issues (e.g. inverted filling priority),
> but there is one that needs discussion:
>
> In pcbnew, each zone
> Hi,
>
> Lachlan sent me a complex board in Eagle that has several copper zones,
> each with different clearances, which filled incorrectly or didn't fill
> at all. There were some trivial issues (e.g. inverted filling priority),
> but there is one that needs discussion:
>
> In pcbnew, each zone
2017-05-01 0:32 GMT+02:00 Tomasz Wlostowski :
> On 30.04.2017 21:02, Lachlan Audas wrote:
>> Here's the link,
>> http://www.cosmosc.com/example/A10-A20-OLINUXINO-MICRO-4GB_Rev_D.brd
>> it's in eagle format, so import under pcbnew.
>> I should of added that viewing the (E)properties and make no cha
I Agree,
Minimum clearance from an edge is not the same thing as minimum
clearance from a trace. Would like to see this also.
The idea to have the zone clearances optionally come from the Design
Rules is also good.
Steven
On 01/05/17 08:28, José Ignacio wrote:
While changing the format it
While changing the format it would also be great if a separate clearance
could be specified between the zone and board edges vs trace clearances, at
least leave the capability in the format if it can't be implemented yet.
I've found that the required copper pullback in some cases is much higher
tha
On 30.04.2017 21:02, Lachlan Audas wrote:
> Here's the link,
> http://www.cosmosc.com/example/A10-A20-OLINUXINO-MICRO-4GB_Rev_D.brd
> it's in eagle format, so import under pcbnew.
> I should of added that viewing the (E)properties and make no changes
> (but hitting the OK instead of the Cancel bu
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