Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 13/06/14 18:46, John Beard wrote:
> On 13/06/14 18:35, Lorenzo Marcantonio wrote:
>> On Fri, Jun 13, 2014 at 06:18:44PM +0100, John Beard wrote:
>>> I have not marked the protruding legs on the RA assembly: would this be
>>> helpful, as the assembly drawing is not obviously handed? Something
>>> like:
>>
>> I'd only put the brackets for the pin area (so you can do pin inspection
>> bar, too)
>>  |
>>  |  |
>>
>>|  |
>>|  |
>>|  |
>>---^
>>  / \
> 
> Is this all assembly layer? If so, do you think the assembly layer arrow
> should point upwards on the SMDs? The IPC assembly layer arrows don't
> extend beyond the body line.

Attached is a PNG of the SMD footprint with bars on the assembly layer,
but with a downward arrow. What do you think? Pink assembly over red
pads is not terribly clear, but you can just about make it out!
Obviously when the assembly layer is printed by itself, this is not an
issue.

John
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 13/06/14 18:35, Lorenzo Marcantonio wrote:
> On Fri, Jun 13, 2014 at 06:18:44PM +0100, John Beard wrote:
>> I have not marked the protruding legs on the RA assembly: would this be
>> helpful, as the assembly drawing is not obviously handed? Something
>> like:
> 
> I'd only put the brackets for the pin area (so you can do pin inspection
> bar, too)

Sorry, I don't quite understand "pin inspection bar"?

>  |
>  |  |
>
>|  |
>|  |
>|  |
>---^
>  / \

Is this all assembly layer? If so, do you think the assembly layer arrow
should point upwards on the SMDs? The IPC assembly layer arrows don't
extend beyond the body line.

>> I have added a little triangle arrow at pin 1 for all types, as I think
>> this is a helpful thing for hand-assembly. I always appreciate it,
>> anyway!
> 
> It's even better if the arrow is visible with the connector soldered, so
> it's faster to attach the cable, too. Especially if the connector is
> *not* polarized. Picoblades (and spoxs) are polarized and pin 1 is marked
> on the body but it's easier to see if it's marked on the silk.

The silk screen is put so it can be seen after soldering. The ASCII art
arrow is an assembly layer feature, modelled after the IPC standard.

> 
> When you have many connectors you can actually reduce assembly time with
> these little things.

Agreed, even with the IPC-style silks, I think the arrow has extra value.

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Fri, Jun 13, 2014 at 06:18:44PM +0100, John Beard wrote:
> I have not marked the protruding legs on the RA assembly: would this be
> helpful, as the assembly drawing is not obviously handed? Something
> like:

I'd only put the brackets for the pin area (so you can do pin inspection
bar, too)

> I have added a little triangle arrow at pin 1 for all types, as I think
> this is a helpful thing for hand-assembly. I always appreciate it,
> anyway!

It's even better if the arrow is visible with the connector soldered, so
it's faster to attach the cable, too. Especially if the connector is
*not* polarized. Picoblades (and spoxs) are polarized and pin 1 is marked
on the body but it's easier to see if it's marked on the silk.

When you have many connectors you can actually reduce assembly time with
these little things.

 |
 |  |
   
   |  |
   |  |
   |  |
   ---^
 / \

-- 
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Logos Srl

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 05/06/14 08:38, John Beard wrote:
On Tue, Jun 03, 2014 at 09:44:53AM +0100, John Beard wrote:
> 
> Here is a more up-to-date version of what I have so far. These Molex
> PicoBlades are specific instances of more general part generators that
> I'm working on.

New version at:

   https://github.com/johnbeard/Connectors_Molex.pretty/tree/picoblades

Attached is an image of the 4 styles.

> I have added an assembly layer on F.Adhes (easy to swap out later if
> needed). I am not sure what the assembly layer for the SMD components
> (with the little "wings") should look like.

The wings now look like this:

  
  | \ /  |
  |  v   |
  |  |
  

I have not marked the protruding legs on the RA assembly: would this be
helpful, as the assembly drawing is not obviously handed? Something
like:

||   ||   ||
  
  | \ /  |
  |  v   |
  |  |
  

> Do you think a line/dot on the silk screen is a good idea?

I have added a little triangle arrow at pin 1 for all types, as I think
this is a helpful thing for hand-assembly. I always appreciate it,
anyway!

If people think these are OK, I will go ahead and make the same for
other ranges (e.g. Harwin M40) which have the same general form. I much
rather get this one range nailed down so that all the others can follow
trivially and without too much in the way of changes, which would get
tedious if there are many modules to change in the same way. For example
making the pin 1 marking 50% bigger in each file!

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Carl Poirier]

Thanks for the clarifications. I will commit that shortly.


On Sun, Jun 8, 2014 at 11:35 AM, Jean-Paul Louis  wrote:

> Let’s get back to the basics.
>
> WHY A SILKSCREEN?
>
> Originally, PCB were assembled by hand, and the markings were dual
> purpose, Assembly and Inspection.
> They were printed on the PCB using colored paint and silk (plastic) or
> metal screens, So the outline of the component was helping the operators to
> stuff the board, and the RefDes was to make sure you were using the right
> part, and also for trouble-shooting a failed test.
> When the board is fully assembled, the outline is meaningless, only the
> RefDes keep its value.
>
> And there is no difference in purpose between Through Hole and Surface
> Mounted parts.
> For polarized capacitors, I have seen a lot of different options, the most
> efficient one being a circle or a square with a “+” sign to show the
> polarity, The “+” sign or sometimes a dot being outside the shape.
> What is important is that the marking eliminate ambiguity, but does not
> jeopardize reliability. So it is VERY important that it does not touch or
> cover a solder area.
>
> my $0.02,
>
> Jean-Paul
> AC9GH
>
>
> On Jun 8, 2014, at 11:14 AM, Carl Poirier 
> wrote:
>
> > About these rules for the silkscreen, are they only for SMD? I am under
> the impression it does not apply well to THT components, for example an
> electrolytic capacitor where we often see a circle with one half full to
> indicate polarity. This would be partly hidden once the board is assembled.
> >
> >
> > On Thu, Jun 5, 2014 at 5:24 PM, Bernd Wiebus 
> wrote:
> > Hello Pawel.
> >
> > Am Montag, den 02.06.2014, 09:57 +0200 schrieb Paweł Dras:
> >
> > > With pads over the silk is the same situation, in many cases after
> > > silk erasure by solder mask it don't looks good on final product.
> >
> > It is not only about "looking good". Silkscreen print over Pads is
> > nasty, if someone forgets to distract the pads from the silkscreen.
> > It may be expensiv, but shure will cost time at last.
> >
> > If you place your silksceen across pads, and erase it over the pads,
> > your silkscreen will be chopped. so better you chopp it by yourself and
> > make it looking good.
> >
> >
> > > Another problem is to wide placed silk.
> >
> > Think about, that you perhaps need place for rework tools.
> > And wave soldering needs more space around the devices than reflow.
> >
> > Some years ago, KiCad insisted in thik lines, because you could not
> > change the wide of silk screen lines. Of course, it was possible by
> > editing the library file by hand.
> >
> > But this thick lines are sometimes needed, because a manufacturer who
> > use a real silk-screen printing process and not a optical process, meeds
> > the wide lines.
> >
> > So bee careful, if you use thin lines. Think about the spacing.
> >
> > > I have a question, can be ref and value placed as in my attachment or
> > > should  be above and below resistor?
> >
> > It is a bad idea, to place text under devices, because it cannot be read
> > anymore, if the device is once mounted..so i put text to this
> > positions, only if there is nowhere a better place for the text.
> >
> > Personally, i switch the value at layouts and silkscreens to invisible,
> > and keep only reference as a designator.
> >
> > Having reference AND value at the layout costs place and is terrible to
> > read. So better i use only the reference, and the BOM of course. ;O)
> >
> > For big boards with few devices, it migt be ok to have both, but for
> > growing sisze, it will get diffcult to read.
> >
> > the exeption is, if you use the silk-screen not as an silk-screen at the
> > board, but as an assembly layer. So you are not stuck to board
> > dimensions, but can make DIN A2 prints for boards the size of a small
> > stamp. ;O)
> >
> > With best regards: Bernd Wiebus alias dl1eic
> >
> >
> >
> >
> >
> > --
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> > Post to : kicad-lib-committers@lists.launchpad.net
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Jean-Paul Louis]

Let’s get back to the basics.

WHY A SILKSCREEN?

Originally, PCB were assembled by hand, and the markings were dual purpose, 
Assembly and Inspection.
They were printed on the PCB using colored paint and silk (plastic) or metal 
screens, So the outline of the component was helping the operators to stuff the 
board, and the RefDes was to make sure you were using the right part, and also 
for trouble-shooting a failed test.
When the board is fully assembled, the outline is meaningless, only the RefDes 
keep its value.

And there is no difference in purpose between Through Hole and Surface Mounted 
parts.
For polarized capacitors, I have seen a lot of different options, the most 
efficient one being a circle or a square with a “+” sign to show the polarity, 
The “+” sign or sometimes a dot being outside the shape.
What is important is that the marking eliminate ambiguity, but does not 
jeopardize reliability. So it is VERY important that it does not touch or cover 
a solder area.

my $0.02,

Jean-Paul
AC9GH


On Jun 8, 2014, at 11:14 AM, Carl Poirier  wrote:

> About these rules for the silkscreen, are they only for SMD? I am under the 
> impression it does not apply well to THT components, for example an 
> electrolytic capacitor where we often see a circle with one half full to 
> indicate polarity. This would be partly hidden once the board is assembled.
> 
> 
> On Thu, Jun 5, 2014 at 5:24 PM, Bernd Wiebus  wrote:
> Hello Pawel.
> 
> Am Montag, den 02.06.2014, 09:57 +0200 schrieb Paweł Dras:
> 
> > With pads over the silk is the same situation, in many cases after
> > silk erasure by solder mask it don't looks good on final product.
> 
> It is not only about "looking good". Silkscreen print over Pads is
> nasty, if someone forgets to distract the pads from the silkscreen.
> It may be expensiv, but shure will cost time at last.
> 
> If you place your silksceen across pads, and erase it over the pads,
> your silkscreen will be chopped. so better you chopp it by yourself and
> make it looking good.
> 
> 
> > Another problem is to wide placed silk.
> 
> Think about, that you perhaps need place for rework tools.
> And wave soldering needs more space around the devices than reflow.
> 
> Some years ago, KiCad insisted in thik lines, because you could not
> change the wide of silk screen lines. Of course, it was possible by
> editing the library file by hand.
> 
> But this thick lines are sometimes needed, because a manufacturer who
> use a real silk-screen printing process and not a optical process, meeds
> the wide lines.
> 
> So bee careful, if you use thin lines. Think about the spacing.
> 
> > I have a question, can be ref and value placed as in my attachment or
> > should  be above and below resistor?
> 
> It is a bad idea, to place text under devices, because it cannot be read
> anymore, if the device is once mounted..so i put text to this
> positions, only if there is nowhere a better place for the text.
> 
> Personally, i switch the value at layouts and silkscreens to invisible,
> and keep only reference as a designator.
> 
> Having reference AND value at the layout costs place and is terrible to
> read. So better i use only the reference, and the BOM of course. ;O)
> 
> For big boards with few devices, it migt be ok to have both, but for
> growing sisze, it will get diffcult to read.
> 
> the exeption is, if you use the silk-screen not as an silk-screen at the
> board, but as an assembly layer. So you are not stuck to board
> dimensions, but can make DIN A2 prints for boards the size of a small
> stamp. ;O)
> 
> With best regards: Bernd Wiebus alias dl1eic
> 
> 
> 
> 
> 
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Carl Poirier]

About these rules for the silkscreen, are they only for SMD? I am under the
impression it does not apply well to THT components, for example an
electrolytic capacitor where we often see a circle with one half full to
indicate polarity. This would be partly hidden once the board is assembled.


On Thu, Jun 5, 2014 at 5:24 PM, Bernd Wiebus  wrote:

> Hello Pawel.
>
> Am Montag, den 02.06.2014, 09:57 +0200 schrieb Paweł Dras:
>
> > With pads over the silk is the same situation, in many cases after
> > silk erasure by solder mask it don't looks good on final product.
>
> It is not only about "looking good". Silkscreen print over Pads is
> nasty, if someone forgets to distract the pads from the silkscreen.
> It may be expensiv, but shure will cost time at last.
>
> If you place your silksceen across pads, and erase it over the pads,
> your silkscreen will be chopped. so better you chopp it by yourself and
> make it looking good.
>
>
> > Another problem is to wide placed silk.
>
> Think about, that you perhaps need place for rework tools.
> And wave soldering needs more space around the devices than reflow.
>
> Some years ago, KiCad insisted in thik lines, because you could not
> change the wide of silk screen lines. Of course, it was possible by
> editing the library file by hand.
>
> But this thick lines are sometimes needed, because a manufacturer who
> use a real silk-screen printing process and not a optical process, meeds
> the wide lines.
>
> So bee careful, if you use thin lines. Think about the spacing.
>
> > I have a question, can be ref and value placed as in my attachment or
> > should  be above and below resistor?
>
> It is a bad idea, to place text under devices, because it cannot be read
> anymore, if the device is once mounted..so i put text to this
> positions, only if there is nowhere a better place for the text.
>
> Personally, i switch the value at layouts and silkscreens to invisible,
> and keep only reference as a designator.
>
> Having reference AND value at the layout costs place and is terrible to
> read. So better i use only the reference, and the BOM of course. ;O)
>
> For big boards with few devices, it migt be ok to have both, but for
> growing sisze, it will get diffcult to read.
>
> the exeption is, if you use the silk-screen not as an silk-screen at the
> board, but as an assembly layer. So you are not stuck to board
> dimensions, but can make DIN A2 prints for boards the size of a small
> stamp. ;O)
>
> With best regards: Bernd Wiebus alias dl1eic
>
>
>
>
>
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Bernd Wiebus]

Hello Pawel.

Am Montag, den 02.06.2014, 09:57 +0200 schrieb Paweł Dras:

> With pads over the silk is the same situation, in many cases after
> silk erasure by solder mask it don't looks good on final product.

It is not only about "looking good". Silkscreen print over Pads is
nasty, if someone forgets to distract the pads from the silkscreen.
It may be expensiv, but shure will cost time at last.

If you place your silksceen across pads, and erase it over the pads,
your silkscreen will be chopped. so better you chopp it by yourself and
make it looking good.


> Another problem is to wide placed silk.

Think about, that you perhaps need place for rework tools.
And wave soldering needs more space around the devices than reflow.

Some years ago, KiCad insisted in thik lines, because you could not
change the wide of silk screen lines. Of course, it was possible by
editing the library file by hand.

But this thick lines are sometimes needed, because a manufacturer who
use a real silk-screen printing process and not a optical process, meeds
the wide lines.

So bee careful, if you use thin lines. Think about the spacing.

> I have a question, can be ref and value placed as in my attachment or
> should  be above and below resistor?

It is a bad idea, to place text under devices, because it cannot be read
anymore, if the device is once mounted..so i put text to this
positions, only if there is nowhere a better place for the text.

Personally, i switch the value at layouts and silkscreens to invisible,
and keep only reference as a designator.

Having reference AND value at the layout costs place and is terrible to
read. So better i use only the reference, and the BOM of course. ;O)

For big boards with few devices, it migt be ok to have both, but for
growing sisze, it will get diffcult to read.

the exeption is, if you use the silk-screen not as an silk-screen at the
board, but as an assembly layer. So you are not stuck to board
dimensions, but can make DIN A2 prints for boards the size of a small
stamp. ;O)

With best regards: Bernd Wiebus alias dl1eic





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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 03/06/14 09:59, Lorenzo Marcantonio wrote:
> On Tue, Jun 03, 2014 at 09:44:53AM +0100, John Beard wrote:
>> How about this for an example of how the SMD headers would look? I
>> haven't added the dot/arrow yet, but it basically uses the line
>> extension at pin 1 idiom from the slides you linked.
> 
> Works for me, could be a good compromise.

Here is a more up-to-date version of what I have so far. These Molex
PicoBlades are specific instances of more general part generators that
I'm working on.

I have added an assembly layer on F.Adhes (easy to swap out later if
needed). I am not sure what the assembly layer for the SMD components
(with the little "wings") should look like.

Do you think a line/dot on the silk screen is a good idea?

Cheers,

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Tue, Jun 03, 2014 at 06:43:21PM +0300, Vesa Solonen wrote:
> Lorenzo, I don't remember why your extended layers system didn't get
> merged. How about reworking it a bit to help CERN work package 4 [1]?

Step 1: get the core devel to accept a change to the layer types and
extend the file format (not a big extension, actually...)
Step 2: decide how to represent the layer mask for pads/how to assign
layer numbers (i.e. how the layer 'name'=>number is happening)
Step 3: ??? (work of mine)
Step 4: profit

Last time we tried there was no agreement on 2) and fierce Dick
obstruction to 1). Resolve these and I can do a good part of 3 (except
for the dialog UI, which I simply don't know how to do...). The layer
setup dialog would be a *big* mess to fix.

I already have several board in full production with the extended layers
but keeping the branch merged is not a lot of fun...

-- 
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Logos Srl

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Vesa Solonen]

03/06/14 11:44, John Beard kirjoitti:

> How about this for an example of how the SMD headers would look? I
> haven't added the dot/arrow yet, but it basically uses the line
> extension at pin 1 idiom from the slides you linked.

I think this is really neat.

> If in future we had a way to add assembly data, the graphic of the
> connector could be added to that.

Lorenzo, I don't remember why your extended layers system didn't get
merged. How about reworking it a bit to help CERN work package 4 [1]?

-Vesa


[1] http://www.ohwr.org/projects/cern-kicad/wiki/WorkPackages


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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Carl Poirier]

I like it!

I will write this down in the convention shortly if that's what we settle
for.


On Tue, Jun 3, 2014 at 4:59 AM, Lorenzo Marcantonio <
l.marcanto...@logossrl.com> wrote:

> On Tue, Jun 03, 2014 at 09:44:53AM +0100, John Beard wrote:
> > How about this for an example of how the SMD headers would look? I
> > haven't added the dot/arrow yet, but it basically uses the line
> > extension at pin 1 idiom from the slides you linked.
>
> Works for me, could be a good compromise.
>
>
> --
> Lorenzo Marcantonio
> Logos Srl
>
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Tue, Jun 03, 2014 at 09:44:53AM +0100, John Beard wrote:
> How about this for an example of how the SMD headers would look? I
> haven't added the dot/arrow yet, but it basically uses the line
> extension at pin 1 idiom from the slides you linked.

Works for me, could be a good compromise.


-- 
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Logos Srl

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 03/06/14 07:42, Lorenzo Marcantonio wrote:


Seems a good starting point to me. Also advanced fabrication requires
often custom-made modules anyway.


How about this for an example of how the SMD headers would look? I
haven't added the dot/arrow yet, but it basically uses the line
extension at pin 1 idiom from the slides you linked.

If in future we had a way to add assembly data, the graphic of the
connector could be added to that.

This way *does* make it much easier to generate new connectors
programmatically, as there are fewer parameters.

John
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Mon, Jun 02, 2014 at 10:24:22PM +0100, John Beard wrote:
> But if it were, it wouldn't be part of the actual board, or have I
> misunderstood? So it wouldn't increase the actual cost of a unit, but is
> rather used for having a reference document to hand (presumably
> partnered with the BOM)?

Yes, it's only for assembly documentation (for checking the pick and
place machine and/or manual assembly reworking)

> PicoBlades. I think a lot of people using KiCad (like me) are not using
> very advanced fabrication technologies!

Seems a good starting point to me. Also advanced fabrication requires
often custom-made modules anyway.

> >There is another reason for courtyard excess, namely reworking
> >clearance. BGAs have extra courtyard because the desoldering nozzle is
> >big!
> 
> I was thinking more of last time I tried to manually hot-air reflow a
> joint that was too close to a plastic header and melted it out of shape.
> Why make those out of such low-melting-temperature and combustible
> material, I ask! ;-)

Because it's designed to run on a wave solder, usually (and anyway peak
reflow in the oven is 260°C, while hot air is usually in the 300-380°C
range)... also you can lower the needed hot air temperature preheating the
board to about 100-120°C (aoyue makes good stuff for that :P)
and/or heat shield the delicate parts (there is special tape for that
but scrap FR4 pieces are good enough).

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Carl Poirier]

Nothing like that yet AFAIK.


On Mon, Jun 2, 2014 at 6:55 PM, John Beard  wrote:

> On 02/06/14 23:21, Carl Poirier wrote:
>
>> About the footprint names, this is a specific device. As per rules 9.x
>> you just go with the name and part number.
>>
>> Connector_Molex_PicoBlade_53398-0271.kicad_mod
>>
>
> Great, thanks! And so I think  the right-angle, SMD, shrouded, etc.
> variant parts are considered specified by the part number, and can be
> expanded in the description?
>
> Is there any sort of style preference for the descriptions? Something
> like:
>
>Molex PicoBlade shrouded wire-to-board header. SMD, vertical, 4 ways.
>
> Is there a preference for terminology w.r.t. ways/circuits/pins/
> something else?
>
> Thanks,
>
>
> John
>
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 02/06/14 23:21, Carl Poirier wrote:

About the footprint names, this is a specific device. As per rules 9.x
you just go with the name and part number.

Connector_Molex_PicoBlade_53398-0271.kicad_mod


Great, thanks! And so I think  the right-angle, SMD, shrouded, etc.
variant parts are considered specified by the part number, and can be
expanded in the description?

Is there any sort of style preference for the descriptions? Something
like:

   Molex PicoBlade shrouded wire-to-board header. SMD, vertical, 4 ways.

Is there a preference for terminology w.r.t. ways/circuits/pins/
something else?

Thanks,

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Carl Poirier]

About the footprint names, this is a specific device. As per rules 9.x you
just go with the name and part number.

Connector_Molex_PicoBlade_53398-0271.kicad_mod


On Mon, Jun 2, 2014 at 6:06 PM, John Beard  wrote:

> On 02/06/14 22:37, Jean-Paul Louis wrote:
>
>> I was talking about the engineering cost to remove any silk screen
>> lines from the soldering pads, not the cost of the silk-screen layer
>> by itself. There is a small cost added if you want markings on your
>> board.
>>
>
> But the fabrication/assembly layer (yellow in Lorenzo's drawing) is not
> a silk screen layer? Isn't it a reference layer that is not part of the
> physical board, or have I misunderstood? I do realise that the
> fabrication layer is not supported in KiCad, I am speaking
> hypothetically anyway.
>
>  Often, people who do not make a living designing boards, do not
>> realize that everything they ask for, often can be done at a cost.
>> But the added cost might be prohibitive for a small number of boards.
>>
>
> I am one of those amateurs, I must admit, and did not know it can cost
> more to exclude a silk screen from pads. No such thing as a free lunch,
> I suppose. I will be more careful in future!
>
> Thank you for your advice,
>
>
> John
>
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 02/06/14 22:37, Jean-Paul Louis wrote:

I was talking about the engineering cost to remove any silk screen
lines from the soldering pads, not the cost of the silk-screen layer
by itself. There is a small cost added if you want markings on your
board.


But the fabrication/assembly layer (yellow in Lorenzo's drawing) is not
a silk screen layer? Isn't it a reference layer that is not part of the
physical board, or have I misunderstood? I do realise that the
fabrication layer is not supported in KiCad, I am speaking
hypothetically anyway.


Often, people who do not make a living designing boards, do not
realize that everything they ask for, often can be done at a cost.
But the added cost might be prohibitive for a small number of boards.


I am one of those amateurs, I must admit, and did not know it can cost
more to exclude a silk screen from pads. No such thing as a free lunch,
I suppose. I will be more careful in future!

Thank you for your advice,

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 31/05/14 12:37, John Beard wrote:

I'm working on the THT Right-Angle Molex Picoblade headers. I have a
question about the silk screen.


The silk screen discussion continues apace, but I also would like to
know about naming:


Another question is what should I do with the names? The convention
document isn't that clear about connectors. Currently, they look like

   MOLEX_53398-0271_2PIN_SMD_VERT.kicad_mod

I am planning to change to:

   Molex_PicoBlade_53398-0271_2Pin_SMD_Vert.kicad_mod

I think it is useful to have the range name in there, as opposed to
just the part numbers, to make it easier to find in the list (then
PicoBlade modules sort together, as do MicroFit and so on). The part
numbers are not sequential in the range: we have 53047, 53048, 53261
and 53398. It's a bit longer, however.


Does this sound like a sensible naming structure for connectors, or at
least connectors which are not some manufacturer-independent standard
(like SOT-XX), but are rather some unique design for each range?

Thanks,

John


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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 02/06/14 20:18, Lorenzo Marcantonio wrote:

On Mon, Jun 02, 2014 at 07:34:12PM +0100, John Beard wrote:

What is the cost of the yellow layer?


The 'cost' of the fabrication layer is simply the full component outline
(99% of the times a rectangle) and a corner line for pin 1. But it's not
supported anyway.


But if it were, it wouldn't be part of the actual board, or have I
misunderstood? So it wouldn't increase the actual cost of a unit, but is
rather used for having a reference document to hand (presumably
partnered with the BOM)?


It's not really a constraint, they simply tell you: if it's smaller
I don't guarantee a thing (and proceed with a 0.2mm line:D). So small
refdes come out as ink blobs


Well, a practical lower limit rather than constraint. But would that be
a good "default" value for the major silk lines and text? I used 0.2 for
the outline and 0.15mm for the text in my first attempt at the
PicoBlades. I think a lot of people using KiCad (like me) are not using
very advanced fabrication technologies!


Physical-collison-detecting DRC sounds handy - I nearly put a resistor
under a QFP on my first KiCad PCB!


It happens with very big components too (thing about heatsinks). Don't
worry it's a common mistake (however you can usefully nest the gate
resistor in the lower space of a D3PAK, right beside the pin...)


Good to know, I'll keep that in mind!


There is another reason for courtyard excess, namely reworking
clearance. BGAs have extra courtyard because the desoldering nozzle is
big!


I was thinking more of last time I tried to manually hot-air reflow a
joint that was too close to a plastic header and melted it out of shape.
Why make those out of such low-melting-temperature and combustible
material, I ask! ;-)

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Mon, Jun 02, 2014 at 07:34:12PM +0100, John Beard wrote:
> button. What client do you use?

mutt. Obviously it doesn't handle it (but could be coerced...)

> What is the cost of the yellow layer? It seems to me to show some useful
> information (the nominal physical presence of the component, including
> the extent of pad overlap) without actually being printed onto the board
> and needing silkscreen, ink, etc. Unless you mean cost to the
> librarians, in which case I think this c/should be optional (assuming
> there was software support in the first place)?

The 'cost' of the fabrication layer is simply the full component outline
(99% of the times a rectangle) and a corner line for pin 1. But it's not
supported anyway.

> And maybe we could say the general silk screen border width is 0.2mm,
> if this a known constraint of fabricators using silk-screens to do the
> silk screen layer?

It's not really a constraint, they simply tell you: if it's smaller
I don't guarantee a thing (and proceed with a 0.2mm line:D). So small
refdes come out as ink blobs

> > some CAD system (the mentor ones, I guess, since they somewhat
> > invented it) actually do DRC on courtyard to avoid collision and such.
> 
> Physical-collison-detecting DRC sounds handy - I nearly put a resistor
> under a QFP on my first KiCad PCB!

It happens with very big components too (thing about heatsinks). Don't
worry it's a common mistake (however you can usefully nest the gate
resistor in the lower space of a D3PAK, right beside the pin...)

There is another reason for courtyard excess, namely reworking
clearance. BGAs have extra courtyard because the desoldering nozzle is
big!

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 02/06/14 16:22, Lorenzo Marcantonio wrote:
> Ach... wrong list. Isn't there a way to set the reply-to address for the
> mailing lists?!

There's a "List-Post: "
header in the email source, and Thunderbird gives me a "Reply List"
button. What client do you use?

> On Mon, Jun 02, 2014 at 10:32:18AM -0400, Jean-Paul Louis wrote:
>> The example shown by Lorenzo is a very good example. The yellow
>> rectangle has zero value AND an extra cost, while just two lines
>> (shown in white) provide the real value of locating the chip without
>> hindering the manufacturing process.  

What is the cost of the yellow layer? It seems to me to show some useful
information (the nominal physical presence of the component, including
the extent of pad overlap) without actually being printed onto the board
and needing silkscreen, ink, etc. Unless you mean cost to the
librarians, in which case I think this c/should be optional (assuming
there was software support in the first place)?

>> On top to it, because it is just inside the guard area (outside
>> rectangle), it provide guidance for the clearance between parts.

But it doesn't help with end-to-end clearance, only side-to-side.

> In fact the specs says that silk should be on the 'maximum material'
> position. I don't remember if I drawn them that way. Anyway the idea
> is that silk should be visible after assembly for inspection, this is
> the *new* primary purpose of the silk. The *old* one, guidance for
> assembly, is mostly obsolete (machines read fiducials, not silk
> screen)

So, for now, I'm thinking that I should focus on a "simple" silk screen
skirting the maximum material condition of the component, with some
extension (and maybe dot/arrow) at pin 1? This would make footprint
wizards somewhat simpler, certainly. "Fancy" drawings could come later
if there is a place for them.

And maybe we could say the general silk screen border width is 0.2mm,
if this a known constraint of fabricators using silk-screens to do the
silk screen layer?

> some CAD system (the mentor ones, I guess, since they somewhat
> invented it) actually do DRC on courtyard to avoid collision and such.

Physical-collison-detecting DRC sounds handy - I nearly put a resistor
under a QFP on my first KiCad PCB!

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Paweł Dras]

IMHO some rules according to silk should be specified in convention. For
example line width should be the same (perhaps with some exceptions) in
whole library, because then the PCB looks clean and more "professional".
With pads over the silk is the same situation, in many cases after silk
erasure by solder mask it don't looks good on final product.

Another problem is to wide placed silk.
For example in attachment is how looks now silk for 1206 resistor and my
proposal for new one. IMHO the silk should be tight to the pad, because
then when we place few such resistors close to each other we don't get a
mess with silk.

I have a question, can be ref and value placed as in my attachment or
should  be above and below resistor?

[image: Obraz w treści 1]


2014-06-02 8:03 GMT+02:00 Lorenzo Marcantonio :

> On Sun, Jun 01, 2014 at 03:59:01PM -0400, Carl Poirier wrote:
> > Lorenzo, you forgot the attachment. I'm following closely the
> conversation
> > and will add the necessary stuff to the convention. ;)
>
> D'oh! It happens :D
>
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 01/06/14 20:01, Lorenzo Marcantonio wrote:

On Sun, Jun 01, 2014 at 06:08:32PM +0100, John Beard wrote:

OK, so what I did so far (with a "fancy" silk) is not really what we are
after?


Never said so. Probably we never decided the standard for silks :P


No time like the present. Any opinions? Personally, I quite like the
"fancy" silks (or fancy assembly layers), but I also would like to make
sure that there is something visible after assembly, if possible. I
realise the detailed silk is more work, so I don't think it should be
any sort of requirement.


That's the real issue for kicad. Since they rejected the
assembly/fabrication layer (and courtyard, too), there is no way to show
the 'full' placement. For reference I attached how I do modules (with
the extra layer). Dark gray is courtyard, light cyan is silk (only two
bars), dark cyan is fabrication (full body with pin 1 indicated). As
a special case  during fabrication plot the refdes position is forced to
the module origin (since the refdes on silk usually is put on a more
visible place).


I didn't see an attachment, could you re-send?


Without the assembly layer the only choice would be using the 'fancy'
silk, and trust silk erasure by solder mask. Really, the two layers
convey different information in different ways, I don't have a good idea
on how to fix this.


I have never registered erasure of silk over pads as a problem, no
fabricator has ever complained or delivered over-printed pads. Has
anyone seen this happen?

How about include an "outer" silk, which is the uneven-U shape and the
pin 1 identifier, along with, optionally, the "inner" silk, which is the
"fancy" outline and would be covered or mostly covered by the component
when assembled.  When hand assembled by hobbyists and amateurs (like
me!) at least, having a nice graphic of what is going in that spot
can be helpful.


There could be also problems with component hanging over the board
size (like shaft potentiometers); these should go on fabrication but
not on silk: AFAIK pcbnew doesn't trim silk on board edges, the
fabricator/panelizer has to do that.


I have never had a problem with fabricators and overhanging silk, I
imagine it's fairly easily dealt with as a matter of course?


the Library Expert screenshot? How would that work for the SMD
variants, which have large "wings" for mechanical strength? Would the
"U" go outside these, to the left and right?


Yep, a tipical SOIC only has silk bars on the short side, outside the
body, with the pin 1 side longer for inspection. See attachment, too.


I meant for these SMD connector headers. The Library Expert Lite
software doesn't seem to include these?


I also like the arrow method, or a dot, as you can see.



Just a stylistic preference. It's however useful since it actually
happened to me to receive ribbons crimped backwards... having the pin
1 triangle really help to see that the red wire is on the wrong side!
For other connectors (like D-sub) it's not very useful, for
rectangular non-polarized obviously it's mandatory.


Indeed. I would even put it on a D-sub, just so its right there when I
need it! The last thing needed when fiddling with cable harnesses is a
last-second self-doubt over the PCB pin location!

Cheers,

John

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Sun, Jun 01, 2014 at 06:08:32PM +0100, John Beard wrote:
> OK, so what I did so far (with a "fancy" silk) is not really what we are
> after?

Never said so. Probably we never decided the standard for silks :P
AFAIK the C revision is the first industry standard about it (and it
isn't a standard yet, anyway). It all depends on what you need from the
silk. In these days it has 3 major purposes:

1) Helping for board connection and major component identification (i.e.
where is that connector and what is pin 1); this is post board assembly
and the important things are refdes and pin 1 marker for connectors (or
the little triangle/arrows/dots whatever)

2) Pre/during/post assembly inspection, when not completely automated.
AOI simply looks for fiducials and then look at each solder joint;
however usually it doesn't check for pin 1 orientation (could be
difficult or maybe there are other issues). Could happen that a tape was
programmed or mounted in the wrong direction, so at least for the first
piece after place checking orientation could be a good idea. In the past
there was a recommendation for the 'inspection dot' on pin 1; this
evolved in the inspection line (along pin 1) or boundary break which are
obviously more visible. The last thing silk is useful for is checking
registration of stenciling and placement; that's why they say that the
outline should be visible with the component placed: if it isn't it's
dropped badly (paste registration is usually checked on fiducials,
AFAIK)

3) Manual assembly or reworking/repair. This was in the past the main
purpose of silk screen. Even without all the refdes in place (usually
there is simply no place for all of them!), having the boundary brackets
and the pin 1 marker is actually all you need to do the work.

> Or, considering that there's no way to add the "body" information except
> on the silk, should I keep the fancy silk, which is mostly covered by

That's the real issue for kicad. Since they rejected the
assembly/fabrication layer (and courtyard, too), there is no way to show
the 'full' placement. For reference I attached how I do modules (with
the extra layer). Dark gray is courtyard, light cyan is silk (only two
bars), dark cyan is fabrication (full body with pin 1 indicated). As
a special case  during fabrication plot the refdes position is forced to
the module origin (since the refdes on silk usually is put on a more
visible place).

Without the assembly layer the only choice would be using the 'fancy'
silk, and trust silk erasure by solder mask. Really, the two layers
convey different information in different ways, I don't have a good idea
on how to fix this.

There could be also problems with component hanging over the board size
(like shaft potentiometers); these should go on fabrication but not on
silk: AFAIK pcbnew doesn't trim silk on board edges, the
fabricator/panelizer has to do that.

> the component when assembled, but add the uneven "U shape" as seen in
> the Library Expert screenshot? How would that work for the SMD variants,
> which have large "wings" for mechanical strength? Would the "U" go
> outside these, to the left and right?

Yep, a tipical SOIC only has silk bars on the short side, outside the
body, with the pin 1 side longer for inspection. See attachment, too.

> I also like the arrow method, or a dot, as you can see.

Just a stylistic preference. It's however useful since it actually
happened to me to receive ribbons crimped backwards... having the pin
1 triangle really help to see that the red wire is on the wrong side!
For other connectors (like D-sub) it's not very useful, for rectangular
non-polarized obviously it's mandatory.

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Re: [Kicad-lib-committers] Silk screens over pads and naming

[John Beard]

On 31/05/14 13:29, Lorenzo Marcantonio wrote:


Never used picoblades but know the minispoxs, seems more or less done in
the same way. The issue is that pads are going outside the component
body.

OK, the 7531C rule (the 'modern' one and, in fact, the only standard one
even if it isn't published yet) says that silk should be completely
visible after assembly, and provide a reference mark for pin 1.

So I'd draw an U shape around the outer connector body, with the leg
aside pin 1 longer, to mark the pin. The U horizontal tract would be the
connector 'mouth', and *no* silk on the pin side. I also like to put
a cute arrow on pin 1 on the insertion side, to help connector fitting,
but that's a personal preference.


OK, so what I did so far (with a "fancy" silk) is not really what we are
after?

Or, considering that there's no way to add the "body" information except
on the silk, should I keep the fancy silk, which is mostly covered by
the component when assembled, but add the uneven "U shape" as seen in
the Library Expert screenshot? How would that work for the SMD variants,
which have large "wings" for mechanical strength? Would the "U" go
outside these, to the left and right?

I also like the arrow method, or a dot, as you can see.

Cheers,

John
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Re: [Kicad-lib-committers] Silk screens over pads and naming

[Lorenzo Marcantonio]

On Sat, May 31, 2014 at 12:37:39PM +0100, John Beard wrote:
> I'm working on the THT Right-Angle Molex Picoblade headers. I have a
> question about the silk screen.
> 
> If you look at the datasheet, the line of the body intersects the pins
> along the back edge. What should I do about the silkscreen in this case?
> Artificially extend it away from the pads (in which case the SS won't
> look like the body), break the line over pads (in which case a SS-only
> view would be full of disjoint lines), or do what I did for now and run
> the line over the pads. The latter has never caused me a problem before:
> most of 
> modules do this.

No names made, of course :D

Never used picoblades but know the minispoxs, seems more or less done in
the same way. The issue is that pads are going outside the component
body.

OK, the 7531C rule (the 'modern' one and, in fact, the only standard one
even if it isn't published yet) says that silk should be completely
visible after assembly, and provide a reference mark for pin 1.

So I'd draw an U shape around the outer connector body, with the leg
aside pin 1 longer, to mark the pin. The U horizontal tract would be the
connector 'mouth', and *no* silk on the pin side. I also like to put
a cute arrow on pin 1 on the insertion side, to help connector fitting,
but that's a personal preference.

I'm attaching a quick screenshot of the LP calculator (connector size is
wrong, but the idea is correct): thick white is the silk, thin white is
the body. Pink is courtyard and yellow assembly, but they didn't let me
add them to pcbnew...

Hope it clears the issue.

These slides also explains other 7531C rules (including
thickness): 
https://communities.mentor.com/mgcx/servlet/JiveServlet/download/28883-8838/PCB%20Design%20Optimization%20Starts%20in%20the%20CAD%20Library.pdf

Of course everything depends on the target technology... if you are
stuck with 5 wires/mm mesh silk screening you can't do 0.15mm silk lines
(for a nominal enviroment). Yes, 7531C is way too modern for some
commonly used processes...

Did we already agree for the 'standard' target process for the default
lib? the baseline commercial cheap process here in Italy is
twoside/0.2: 0.2mm track, 0.2mm clearance, 0.2mm silk screen, 0.2mm
annulus, minimum drill usually 0.4. I think that in the States this
would be known as a 8 mils process. Gives something like 99% yield, so
it's good :D Pads for pitch 0.5 needs to be trimmed but reliability is
good. Also you can rework and patch them by hand easily, without
particular techniques.

For standard work a 0.15 track/clearance no trim for pitch 0.5, and
drill can be usually done to 0.35/0.3 without too much extra cost. Many
rapid proto PCB houses here do this as a standard service at up to
8 layers.

BGA/fine pitch works usually require 0.1 track clearance (and 4 to
...many layers:D). Custom stackups are usually needed or specified
anyway...  Microvias are laser drilled at 0.2mm, never seen blind via as
a provided service (YMMV obviously); anyway this kind of board is
definitely *not* a quick turnover product :)

I'd say that targeting for a 0.15mm/6 mil process could be a good
starting point for the 'builtin' libraries.

-- 
Lorenzo Marcantonio
Logos Srl
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