--- In firstname.lastname@example.org, axtz4 [EMAIL PROTECTED] wrote: Another option is Veecad from http://www.veecad.com. Thanks for the suggestion, but I forgot to mention that I am running on Linux. It's been pointed out to me on the gEDA mailing list that I could use a script to edit the underlying data files containing my project in order to add the veroboard tracks. It's an approach that I would like to try with Kicad as well. Are there any standard libraries that I can use within my own scripts to edit the newpcb project data files ? I've looked around and can't see anything, but as I am new to Kicad, I may be missing some well known location. Thanks, Simon.
The new format for eeschema appears to be causing problems with local labels, global labels, and the new hierarchical label when generating netlists. I am working with a schematic that several people have been working on. It has a root sheet, a sheet inside the root and another one in the second level sheet. When the netlist was generated nets were merged for no apparent reason and given names that were not specified on any net. The PCB interconnectivity was really screwed up. Fortunately I was able to remove the hierarchy enhancements from the schematic file with a text editor and load it into 2007-11-29 EESchema, it converted a lot of what should have been global labels to text. Once I cleaned these up I was able to generate a correct netlist and start working on the PCB. Any one else had problems Like these with netlist generation from a hierarchical schematic on the new release? I was very concerned with the new release when I saw that the schematics were not backward compatible with the older releases. Now it seems my concerns were justified.