Re: [kicad-users] Removing inner pads with vias
Hi, I am not sure that this is possible. Vias and through hole components have pad for every layer. Try to edit the files with a Gerber editor and trim the pads . Could you send a visual representation of the DRC ? Most likely you will have to rework the problem zones. Regards On Fri, 2008-05-16 at 22:46 +, mkajdas wrote: My PCB house DRC check complains about vias having pads on inner layers. How to have via pads on the outside and no pads inside the board on 4 layer board? The inner pads are not connected to anything and do not hurt anything but I get over 500 errors that I want to clean up. Martin
Re: [kicad-users] Is it posible to split a single multi-part device across sheets?
Hi, Yes it is possible. Just look how opamp symbols are made in Kicad. I think that it is possible to split the part on A B C D subparts. I would use double page size but split the part is a good idea too. Remember to override the automatic part annotation for this part only so you keep it as one footprint. Good luck. On Wed, 2008-04-30 at 07:46 -0700, Mike Panetta wrote: The subject pretty much says it all. I have a part I have made for the LPC2468 with a part for each port. I want to put the 2 ports dedicated to the expansion bus on one sheet and the other ports on another so I can keep the sheets to 8.5x11 for easy printing. Is this possible? If its not I guess I could double the paper size, but I would prefer not to. Thanks, Mike __ Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now.
[kicad-users] Autorouter question
Hello I am using Kicad for almost a year now and i have some questions about the autorouter`s work. Is there a file with settings for the router . And also what is the anneal file. 10X in advance
[kicad-users] Pad question
Hello , I would like to know if there is a way for composite pads creation. For example a copper pad assembled from few copper pads and solder paste pad , that differs from the copper one. For example a power pad witch solder paste is divided in four equal parts and a solder mask pad wich is much bigger or smaller than the copper pad. Is Kicad made in mind for such actions or pad shape is same for all layers? Thank you
Re: [kicad-users] Relation betwen EeSchema and PCBNew
On Sat, 2007-10-20 at 12:23 +, jt.openflyers wrote: Hi I create my schema en built my circuit board But I make a mistake and I want to modify schema, one connector must be in symetrical position On schema I changed my connector with the tool miror Y || and I redrawn all the connexion to this connector But relation with schema and PCB is always the old version and radnest is not conform to my schema Can I regenerate all the link Thank Well 1 Save the updated netsit 2 Load the updated netlist in PCBNEW 3 Compile the netlist This should change nets and components. Cheers
Re: [kicad-users] +VCC and -VCC
On Tue, 2007-10-16 at 21:50 +1000, jeremy wrote: VCC is there in powers I can't find -VCC in Powers. Can I make one somehow? Thank you! Please do not ;) The opposite of Vcc is not -Vcc . It is Vee ! Look here http://encyclobeamia.solarbotics.net/articles/vxx.html -Vcc is used for better explanation only. It means that Vee is same as Vcc and it is with opposite polarity . Good luck !
Re: [kicad-users] Undo ruler
On Mon, 2007-10-15 at 03:47 +, gsun wrote: Hello, I am a new user of Kicad. Is there a undo function in PCBNEW and a ruler displayed with the dimension of the drawing with units choosen? Another small thing, how do I turn on snap-to-grid feature in PCBNEW? TIA Yep the ruler is called Add Coatation and it is on the right menu. Do not use it on copper layers . The display metric or imperial depends on the mm or inch tools on the left menu. There isn`t any Undo feature implemented yet i think , but there is Undelete function . Snap to grid and snap to electrical grid is default turned on. I think that it cannot be turned off exept for magnetic pads which is from the Preferences -- General options menu. Cheers
[kicad-users] Great Idea
Hi 2 all , I have the following idea for very useful KiCad new function : A netlist select function . It will do the following : When pin or label is selected with this function it will go to the netlist file and finds the net name this pin or label is associated with , and popup window in which are displayed the name of the net and pins connected to this net . This resolves many problems with the design verification actually and is very simple to implement. Making this function work with wires will be hard , but for pins and labels it is really simple. I think that this is topic for the devel group , but i wanted to discuss this first . I made a pool about this and will be very greatfull to know what do you think about such function. Please read the Kicad FAQ in the group files section before posting your question. Please post your bug reports here. They will be picked up by the creator of Kicad. Please visit http://www.kicadlib.org for details of how to contribute your symbols/modules to the kicad library. For building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-devel Yahoo! Groups Links * To visit your group on the web, go to: http://groups.yahoo.com/group/kicad-users/ * Your email settings: Individual Email | Traditional * To change settings online go to: http://groups.yahoo.com/group/kicad-users/join (Yahoo! ID required) * To change settings via email: mailto:[EMAIL PROTECTED] mailto:[EMAIL PROTECTED] * To unsubscribe from this group, send an email to: [EMAIL PROTECTED] * Your use of Yahoo! Groups is subject to: http://docs.yahoo.com/info/terms/
Re: [kicad-users] Re: some troubles
Ken Ames wrote: hi Charles, and everyone else. I created a file directory kenames and put those files there. actually, DATA 0-7 goes all over in a complex schematic but the kpicubed-io.sch is where the signals actually originate. there are also address lines in the io that have the same problem, coming off the 74ls541 chips. I really appreciate your help on this and let me know if you need more to help out. (I just don't want to clutter the files area to much.) thanks again, Ken Hi Ken I have noticed a simillar problem this is the mail i have posted BUS bug in multisheet schematics so if the buses are not drawn complietly in the main page (Page1) this could be causing no conn between bus members in different pages. This would rarely be the problem. What could be happening is probably the following: You have entries to a sheet from more than one place. For ex: Can you enter sheet that is herahly part from sheet A from sheet B? If yes this is causing the problems.Remember Kicad hierashy is straight forward and does not support this. Look at this Mainpage | | | | | Page1 | | | Page2 Page3 This is correct But if you have this Mainpage | | | | | Page1 | | | Page2 Page3 | Page1,2 or Mainpage This causes problems Hope that this helps you Sorry i have not looked at the sch files :(
Re: [kicad-users] Re: PCBNEW not refreshing netlist
yajeed2000 wrote: --- In kicad-users@yahoogroups.com mailto:kicad-users%40yahoogroups.com, richmogd [EMAIL PROTECTED] wrote: Hi guys, I'm almost there with my first Schematic/PCB on kicad. However, I'm getting stuck on the PCBNEW netlist read. I read an early version of the netlist to check that the modules and nets were coming in correctly. I've since updated the netlist to change some footprints. However, wehn I re-read the netlist, PCBNEW seems to be reading a cached version of the file. I've looked at the netlist file in a text editor and the file itself is ok, but PCBNEW doesn't appear to be reading from this file as the source. Any idea how I clear the cache and make sure that PCBNEW reads the new file completely? Thanks, Glenn. Hi, Have you tried opening the netlist file in CvPCB and then reimporting the file into PCBNEW? Please try this and see if it works. Regards, David. HI do you compile the netlist after read? it is stupid question but it is possible i had about a 10 corrections in a netlist and everything went right I use Build Version: EESchema (2006-06-26) - Unicode version
Re: [kicad-users] Power Ports - local or global?
apluscw wrote: Are power ports local to a sheet, or are they global across the entire hiearchy? For example, my design has mixed analog and digital 3.3 Volt circuits. My digital circuits are in one sheet, and my analog circuits are in another sheet, all tied together into a hierarchy. If I tie 3.3V to my analog source in my analog sheet, and 3.3V to my digital source in my digital sheet, will they become merged as one node, or will they be two separate nodes (which is the intent)? Thanks, a+ Yes they are global i think look at this 1 VSS ) (2 VDD ) (3 MCLK_1 ) this is part of netlist VSS and VDD are global labels and the MCLK is local label on page 1 Good luck ;)
Re: [kicad-users] Power GND Nets
richmogd wrote: Hi All, I've created a hierarchical schematic layout and have used the 3.3V and GND power components for the power on each page. When I export to netlist, these items are shown as separate nets as opposed to connected together. Do I have to connect each of these to the global 3V3 and GND net via glabels for each page or is there an automated way to make kicad release that all 3V3 connections are for the same net and all GND connections are for the same net? Thanks, Glenn. Hi this cannot be all power symbols are Global I have tryed a test design evaluating KiCad and it was fine. Do you have a power port symbol connected to the power nets thou it is rarely the problem The problem is more likely : You have invisible power pins that EEschema connects automatically like VCC on the one page and VDD on the other and the 3V3 power net . EEschema connects all invisible power pins in groups leaving you to believe Look at the netlist file if the net names are 3v3_1 3v3_2 this means that the are not global see this 1 VSS ) (2 VDD ) (3 MCLK_1 ) vss and vdd are global labels and mclk_1 is label mclk in page 1 this could be a major bug so please investigate further hope you come out of this soon
Re: [kicad-users] Power Ports - local or global?
Yes they are global i think look at this 1 VSS ) (2 VDD ) (3 MCLK_1 ) this is part of netlist VSS and VDD are global labels and the MCLK is local label on page 1 Good luck ;) sorry this was the original message i wrote the first time
[kicad-users] HI A footprint discussion
Hello i use KiCad 4 months now and find it a real modern hi-end CAD system, but i think that the component and footprint databases are not coressponding to the hi-end soul of Kicad. It is obvious that we cant have all the component and footprints present , but i would like to start a discussion about the need of an web service on the Kicad component site for ONLINE search for components , footprints and the upload , download and viewing of them , creating a really big database where everyone could participate and contribute. I know that this is hard to accomplish , but I think that an open discussion about this would be helpful . Cheers p.s. i am not sure is this the right way about adding a new topic on the forum so apologies if i have something stupid
