[kicad-users] Re: change net connection of invisible Pins

2010-03-16 Thread daystar1013
Well, On your two micros, I suggest that you forget ERC and check your NETLIST 
or better yet open the design in PCBNEW and verify that you do indeed have two 
power rails.

--- In kicad-users@yahoogroups.com, Robert birmingham_spi...@... wrote:

 Thanks for your replies Carl and Andy.
 
 Speaking for myself, I have designs that use two instances of the same 
 micro, with each instance on a different supply rail.   These micros all 
 have a power pin named VCC and I have no problems with ERC, so Kicad 
 isn't covertly connecting my VCC pins together.
 
 The OP (Mark) wants to have logic chips on two different supply rails, 
 but it seems that Kicad joins up all the hidden pins marked Vcc, even if 
 you connect the power pin to a different rail.   Is the critical factor 
 that the pins are hidden, is it that the name case sensitive, or is it a 
 feature of multi-part components?   It's not that the pin doesn't have a 
 number, because the logic chip symbols have both name and number 
 specified for the power pins (like the symbols I have created for 
 myself).   What is the critical thing that Mark has to change to allow 
 him to connect two logic chips to two different supply rails.
 
 Regards,
 
 Robert.
 
 
 
 On 16/03/2010 11:14, Andy Eskelson wrote:
  Vcc IS the power to the chip, U2A in this case.
  so why have you connected +5V to it as well?
 
  DRC is detecting that you have effectively shorted VCC  to a different 5V
  supply as well, and is complaining about it.
 
  Power flags are defined as power out pins, and you only have one power
  out on a power net,m if you add a second power flag DRC will complain
  about that as well.
 
  I think you are assuming that you need to connect 5 volts to the chip,
  and so are adding the +5V port, which is another independent supply net.
  Hence the confusion.
 
  The system works as has been mentioned by the power port names. When a
  device has a power pin with a specific name, AND you set the pin to be
  invisible you DO NOT need to connect anything else to it. As soon as you
  put a power port with the same name onto the circuit diagram, that port is
  automatically connected to all device power pins with the same name.
 
 
  A power net needs to be energised or DRC will complain. That can be done
  in two ways. Either a device such as a regulator can have a power out
  pin, which will indicate that it is energised, OR you add a power flag,
  which simply says that the net is energised. You use power flags in
  situations where you are connecting an external power source to your
  circuit via a connector, flying leads and so on.
 
  The one oddity is that GND is considered a power out type net as well, so
  it also needs energising with a power flag.
 
  logic IC's have generally had their power pins identified by names
  rather than the voltage, so you have Vcc Vss Vdd and so on.
 
  When you run into such chips, the same will apply, power ports of the
  same name are already considered to be connected to the physical supply
 
  Andy
 
 
 
 
 
  On Mon, 15 Mar 2010 16:13:15 -
  mthelingp...@...  wrote:
 
  Hi Robert,
 
  if I connect for example a net +5V to a component U2A which has an VCC 
  input as invisible pin, I see that  in PCBnew the pin is connected to the 
  +5V net as soon as I set an Powerflag to +5V.
  But the ERC check in eeschema states this as error :
  ErrType(5): Conflict problem between pins. Severity: error
   @ (5,1000 ,6,7500 ): Cmp #FLG01, Pin 1 (power_out) connected to
   @ (4,4000 ,6,7500 ): Cmp #FLG06, Pin 1 (power_out) (net 3)
 
  If I don't connect a Powerflag to the +5V net, in PCBnew the Power Pin 
  of U2A is still connect to the VCC net and not to +5V as set in the 
  schematic.
  Please see schematic for example:
  http://www.swapout.de/example_schematic.pdf
 
  What I am doing wrong?
 
  Thank you,
 
  best Regards,
  Mark
 
 
 
 
  
 
  Please read the Kicad FAQ in the group files section before posting your 
  question.
  Please post your bug reports here. They will be picked up by the creator 
  of Kicad.
  Please visit http://www.kicadlib.org for details of how to contribute your 
  symbols/modules to the kicad library.
  For building Kicad from source and other development questions visit the 
  kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! 
  Groups Links
 
 
 
 
 
  
 
  Please read the Kicad FAQ in the group files section before posting your 
  question.
  Please post your bug reports here. They will be picked up by the creator of 
  Kicad.
  Please visit http://www.kicadlib.org for details of how to contribute your 
  symbols/modules to the kicad library.
  For building Kicad from source and other development questions visit the 
  kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups 
  Links
 
 
 
 
 
 
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  Checked by AVG - www.avg.com
  

[kicad-users] Re: eeschema 20080715 Netlist Errors

2008-07-31 Thread daystar1013
Jean-Pierre,

I believe I know what happened, it was to some degree a problem with 
mixing eeschema versions between different engineers working on the 
same project.
Two of the sheets were developed separately, one root containing one 
child sheet. We then added that root sheet to another schematic as a 
child sheet. The name of the child sheet that had been the root was 
changed. One of the nets that contained several erroneously merged 
nets had the same name as the previous root schematic. I believe at 
some point in time one of the schematics was manually edited and some 
of the sheet timestamps had been removed. Interestingly enough, 
eeschema still rendered the schematics correctly.
I guess the only complaint I have is the lack of verbose diagnostics 
in the schematic to netlist conversion. I had to find the errors in 
PCB, emitters and collectors of transistors being shorted together 
and the like.

Thanks for your consideration and timely response.

--- In kicad-users@yahoogroups.com, jean-pierre charras jean-
[EMAIL PROTECTED] wrote:

 daystar1013 a écrit :
 
  The new format for eeschema appears to be causing problems with 
local
  labels, global labels, and the new hierarchical label when 
generating
  netlists.
  I am working with a schematic that several people have been 
working on.
  It has a root sheet, a sheet inside the root and another one in 
the
  second level sheet.
  When the netlist was generated nets were merged for no apparent 
reason
  and given names that were not specified on any net. The PCB
  interconnectivity was really screwed up.
 
 New hierarchical labels are the old global labels. the current 
global 
 labels are new and are actually globals (as said in new doc)
 I have no problem with new eeschema labels handling.
 So, can you send me your kicad project ?
 
 
 -- 
 
 Jean-Pierre CHARRAS
 
 Maître de conférences
 Directeur d'études 2ieme année.
 Génie Electrique et Informatique Industrielle 2
 Institut Universitaire de Technologie 1 de Grenoble
 BP 67, 38402 St Martin d'Heres Cedex
 
 Recherche :
 GIPSA-LIS - INPG
 46,  Avenue Félix Viallet
 38031 Grenoble cedex





[kicad-users] eeschema 20080715 Netlist Errors

2008-07-30 Thread daystar1013
The new format for eeschema appears to be causing problems with local 
labels, global labels, and the new hierarchical label when generating 
netlists. 
I am working with a schematic that several people have been working on. 
It has a root sheet, a sheet inside the root and another one in the 
second level sheet.
When the netlist was generated nets were merged for no apparent reason 
and given names that were not specified on any net. The PCB 
interconnectivity was really screwed up.
Fortunately I was able to remove the hierarchy enhancements from the 
schematic file with a text editor and load it into 2007-11-29 EESchema, 
it converted a lot of what should have been global labels to text. Once 
I cleaned these up I was able to generate a correct netlist and start 
working on the PCB.
Any one else had problems Like these with netlist generation from a 
hierarchical schematic on the new release?
I was very concerned with the new release when I saw that the 
schematics were not backward compatible with the older releases. Now it 
seems my concerns were justified.



[kicad-users] Metric Gerber and Drill Files

2008-05-29 Thread daystar1013
Does anyone know if I can produce Metric Gerber and Drill files with 
Kicad?



[kicad-users] Re: How do you route a rats nest?

2008-01-12 Thread daystar1013
--- In kicad-users@yahoogroups.com, tony.payn [EMAIL PROTECTED] wrote:

 Hi
 
 I'm new to kicad (day one) but am finding it generally easy to use.
 
 However I can't see how to manually route a rats nest.  I would like to 
 select a rat and convert it to track manually one segment at a time, 
 clicking on where I want the next vertex.  Is there a way?
 
 I can do it automatically for the whole segment, but sometimes it goes 
 by a route I don't like.  Then it's difficult to move because moving a 
 segment at a time causes rule violations, which means the track can't 
 be easily altered.
 
 Also, how can you make a track change to the opposite side of the board?
 
 Tony

Tony,

Click the 'Display local ratnest' button ( third from the top on the
right side). 
Then click on a pin thats on the net you want to route. 
The single net will be shown as a rats nest. 
Then click the 'Add tracks and vias' button ( fifth from the top on
the right side)
you can now manually route the selected net. You should already have
selected the layer you want the track on and the width of the track.




[kicad-users] Re: COMPILE KICAD ON VISUAL C++ 2005

2008-01-11 Thread daystar1013
--- In kicad-users@yahoogroups.com, Bodann OSLO [EMAIL PROTECTED] wrote:

 Hello,
 
 I'm Menkilah a C++ developer.
 I want help about integrating KiCAD on Visual C++ 2005 and 
compiling it with nmake.exe (makefile.g95).
 I have already try with nmake but there  is  error: d était 
inattendu. NMAKE: fatal error U1077: 'for': return code '0x1' 
 
 What is the problem?
 
 Thanks!
 
 
 
 
 
   

You have a lot of work to do, the GNU make file is not compatible 
with nmake. In Kicad you will find the keyword typeof is used 
throughout the different programs because it is used in a typeless 
swap macro. To overcome this problem you need to install the boost 
libraries and include the typeof emulation headers for MSC_VER  
1310. I wrote an include file that must be included in the main 
header file fctsys.h as #ifdef __MSVC__ #include msvc_kicad.h 
#endif that handles including the boost libraries and takes care of a 
couple of other minor compatibility issues. __MSVC__ must be globally 
defined. If you are using visual C++ 2005 or greater you need to 
include additional make information to handle the side by side 
assemblies required for the operating system to load the application. 
If possible I suggest using Visual C++ .net 2003 to avoid this 
complication. I could provide you with more information if you want 
it, let me know. I have compiled 32 and 64 bit msvc versions using 
2003 .net, 2005, and 2008 versions on MSVC.

Carl


__
___ 
 Ne gardez plus qu'une seule adresse mail ! Copiez vos mails vers 
Yahoo! Mail http://mail.yahoo.fr





[kicad-users] Re: Single layer PCB ... bridges on top layer

2007-12-17 Thread daystar1013
Brian,
I have found a PCB house that specializes in one of a kind PCB, its 
an all notouch/online process. The price for a single two sided board 
( I have made boards up to 8.5 X 4 inches) is under $100 USA. Three 
boards are still under $100.
You register online and then you can submit your gerber files and 
drill files for automatic file verification in a standard zip file. 
You associate layers with files in a web form and then verify the 
hole count/size for plated through holes and wait for verification. 
All you need to do then is give them a credit card number and in four 
working days your board(s) will ship.
The link is http://www.protoexpress.com
Kicad files go through the verification process easily with two 
exceptions, make sure your board edge is 0.010 and DO NOT mirror 
your drill file. When you create the NC drill file the default option 
is to mirror the Y axis, Proto express expects all the files to be 
non-mirrored.
I have made six boards here and everyone worked as designed out of 
the box.

Carl
--- In kicad-users@yahoogroups.com, Brian [EMAIL PROTECTED] wrote:

 I face the same problem. I often make one off PCBs which would be 
 uneconomical to sent to a fab house. Adding Zero ohm resistors is 
an 
 option but as mentioned, you have to add them to the schematic and 
 sometimes remove them as well while working on a PCB layout.
 
 There is also the problem of needing many different footprint 
lengths 
 between pads for the different link lengths.
 
 I've done it in the past by making a double sided design with the 
 links on one side and the tracks on the other but it causes 
problems 
 with via holes and pads for the links to connect to.
 
 Perhaps an option to drop pads instead of vias could be added. That 
 way the double sided method could still be used and the netlist 
would 
 be correct but a pad to solder the link to would be present.
 
 Brian.
 
 
 --- In kicad-users@yahoogroups.com, newskyperhh boris.fiedler@ 
 wrote:
 
  Yes, sure ... but, so i must change my schematic.
  It isn't possible to change the layer, place a pad or something 
else
  and have no trouble by ERC check.
  
  LG
  
  Bo
  
  --- In kicad-users@yahoogroups.com, KeepItSimpleStupid
  keepitsimplestupid@ wrote:
  
   Will 0 ohm resistors work? or Components Like Jx for Jumper 
 Jumper x.
e.g. J1?
   
   --- In kicad-users@yahoogroups.com, newskyperhh 
boris.fiedler@
   wrote:
   
Hello.

I want to make a single layer PCB with only one copper site. 
So 
 i must
make manually bridges on component side.

But I can't make any pad's or continuous bonding / interlayer
connection  for bridges.

I hope anybody can help.

Thank You,

Boris
   
  
 





[kicad-users] Re: Pcbnew Problems

2007-12-13 Thread daystar1013
Dick,
I took your advice on the changes to the way the mouse works. I 
renamed the schematic and generated a new net list and then read it 
into PCBNEW. Everything worked fine. I had become accustomed to 
working with the mouse the way it used to work. I think the 
difference in the OnClick and OnRelease is what got me.

Thanks for the Advice


--- In kicad-users@yahoogroups.com, Dick H. [EMAIL PROTECTED] wrote:

 --- In kicad-users@yahoogroups.com, daystar1013 daystar@ wrote:
 
  I use kicad daily for reverse engineeering and occasionally 
PCBNEW for 
  test fixtures. I have been using the 2007-11-29-RC2 release for 
  Windows, I have not layed out a PCB until today. 
  I started a PCB layout, a small circuit (5X3) with six - 16 pin 
SO14E 
  footprints and two TQFP-44's, 1206 resistors and capacitors, and 
some 
  LEDs. I read the netlist into pcbnew and as usual the parts were 
all 
  stacked up on top of each other, no problem.
  I place the parts manually, I do the entire process manually, 
PCBNEW is 
  an excellent tool for manually routing a PCB. The problem I 
started 
  seeing was that I would move a part, and place it. I would go to 
move 
  the next part, and I would grab the same part off of the stack 
that I 
  just placed. About half the time a part I placed would stay where 
I 
  placed it. I finally gave up and went back to the July release. I 
  completed the board in a couple of hours.
 
 
 
 One of the changes we made in this release involves mouse clicking. 
 (And for a good reason I'll add right up front.  There is no going 
back.)
 
 
 Many of the program's actions happen now on the mouse release,
 whereas they used to happen on a mouse press.  So you might look 
at
 what makes up your environment, including your mouse driver, your
 mouse, and your version of Windows.  Also consider how you are using
 the mouse.
 
 Try slowing down and verifying that when you drop the footprint in
 place, it stays there.
 
 
 Others do not seem to be having this problem.





[kicad-users] Re: Cvpcb crashed, and I can't make it work again!

2007-12-12 Thread daystar1013
I believe this is related to a windows only bug in the 
FootprintListBox constructor. CVPCB will crash because of the use of 
an unitialized pointer in the constructor.

the fix is to add the line

m_ActiveFootprintList = NULL;
to the constructor, line 74 cvpcb/listboxes.cpp

the error occurs in SetActiveFootprintList ...

#ifdef __WINDOWS__
/* Workaround for a curious bug in wxWidgets:
 *  if we switch from a long list of footprints to a short list 
(a filtered footprint list),
 *  and if the selected item is near the end of the long list,
 *  the new list is not displayed from the top of the list box
 */
if ( m_ActiveFootprintList )
{
bool new_selection;
if( FullList ) new_selection = TRUE;
else new_selection = FALSE;
if( new_selection != old_selection )
SetSelection( 0, TRUE ); // the exception 
occurs here
}
--- In kicad-users@yahoogroups.com, jean-pierre charras - INPG jean-
[EMAIL PROTECTED] wrote:

 ahuitzot a écrit :
 
  Since I can't get the yahoo groups search function to work, Ill 
just
  go ahead and post this... I'm sorry if its a duplicate question.
 
  I was working on a project 2 days ago, a simple power supply 
board.
  Everything was going ok, until I decided I would add a 
hierarchical
  sheet to my schematic. Before I did that I had added several
  components to the schematic one at a time and used cvpcb to add 
them
  to the board, with great success. I like to do incremental adds to
  keep from cluttering up the board, so this is why I do it this 
way...
 
  Well anyway, I added the hierarchical sheet and put a LPC2368 on 
it
  from the nxp library I downloaded, and added 2 global net labels. 
I
  also added the same 2 global labels on the main sheet (Is that the
  right way to do it?) I then went to re-annotate my schematic(s) 
and
  create the netlist. This all went ok as it normally had. Next I 
ran
  (or rather tried to run) cvpcb to assign the footprints to the new
  parts. BAM it crashed right away.
 
 Can you send me (or/and send to Dick H.) your files (zip your 
project 
 and send the zipped file).
 
 -- 
 Jean-Pierre CHARRAS
 Maître de conférences
 Directeur d'études 2ieme année.
 Génie Electrique et Informatique Industrielle 2
 Institut Universitaire de Technologie 1 de Grenoble
 BP 67, 38402 St Martin d'Heres Cedex
 
 Recherche :
  Grenoble Image Parole Signal Automatique (GIPSA - INPG)
 46, Avenue Félix Viallet
 38031 Grenoble Cedex





[kicad-users] Pcbnew Problems

2007-12-12 Thread daystar1013
I use kicad daily for reverse engineeering and occasionally PCBNEW for 
test fixtures. I have been using the 2007-11-29-RC2 release for 
Windows, I have not layed out a PCB until today. 
I started a PCB layout, a small circuit (5X3) with six - 16 pin SO14E 
footprints and two TQFP-44's, 1206 resistors and capacitors, and some 
LEDs. I read the netlist into pcbnew and as usual the parts were all 
stacked up on top of each other, no problem.
I place the parts manually, I do the entire process manually, PCBNEW is 
an excellent tool for manually routing a PCB. The problem I started 
seeing was that I would move a part, and place it. I would go to move 
the next part, and I would grab the same part off of the stack that I 
just placed. About half the time a part I placed would stay where I 
placed it. I finally gave up and went back to the July release. I 
completed the board in a couple of hours.