Yes we plan to release patch as soon as we cleaned up the code and we
get the green light from our company ( and sadly it can take month on
that point..)
On 13 January 2012 01:31, Takuya Yoshikawa
yoshikawa.tak...@oss.ntt.co.jp wrote:
(2012/01/13 10:09), Benoit Hudzia wrote:
Hi,
Sorry to
This patch adds the possibility to run commands using the default parameter
in 'lkvm sandbox'. For example, a user would now be able to run:
'lkvm sandbox firefox'
And have a sandboxed firefox instance start in the guest.
For commands with parameters, we still need to use dashdash to
On 13 January 2012 02:03, Isaku Yamahata yamah...@valinux.co.jp wrote:
Very interesting. We can cooperate for better (postcopy) live migration.
The code doesn't seem available yet, I'm eager for it.
On Fri, Jan 13, 2012 at 01:09:30AM +, Benoit Hudzia wrote:
Hi,
Sorry to jump to hijack
On 13 January 2012 02:15, Isaku Yamahata yamah...@valinux.co.jp wrote:
One more question.
Does your architecture/implementation (in theory) allow KVM memory
features like swap, KSM, THP?
* Swap: Yes we support swap to disk ( the page is pulled from swap
before being send over), swap process do
On Fri, Jan 13, 2012 at 7:45 AM, Liu ping fan kernelf...@gmail.com wrote:
On Thu, Jan 12, 2012 at 5:21 PM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Thu, Jan 12, 2012 at 4:38 AM, Liu ping fan kernelf...@gmail.com wrote:
Could anybody give some description about the implement of hyercall in
On Thu, Jan 12, 2012 at 04:56:33PM +0100, Jan Kiszka wrote:
Stephan Baerwolf (2):
KVM: extend struct x86_emulate_ops with get_cpuid
KVM: fix missing illegal instruction-trap in protected modes
arch/x86/include/asm/kvm_emulate.h | 19
arch/x86/kvm/emulate.c
On Thu, Jan 12, 2012 at 06:07:51PM +0100, Julian Stecklina wrote:
Am Freitag, den 23.12.2011, 08:40 -0200 schrieb Marcelo Tosatti:
On Mon, Dec 19, 2011 at 02:14:27AM +0100, Julian Stecklina wrote:
If the guest programs an IPI with level=0 (de-assert) and trig_mode=0
(edge),
it is
This patch series adds support for CPU _EJ0 callback in Seabios and qemu-kvm.
The first patch defines the CPU eject bitmap in Seabios and writes to it
during the callback. The second patch adds empty stub functions to qemu-kvm to
handle the bitmap writes.
The third patch defines the eject method
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
---
src/acpi-dsdt.dsl |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 7082b65..71d8ac4 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
---
hw/acpi_piix4.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index d5743b6..8bf30dd 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -37,6
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
---
hw/acpi_piix4.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 8bf30dd..12eef55 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@
Am Freitag, den 13.01.2012, 08:52 -0200 schrieb Marcelo Tosatti:
On Thu, Jan 12, 2012 at 06:07:51PM +0100, Julian Stecklina wrote:
Am Freitag, den 23.12.2011, 08:40 -0200 schrieb Marcelo Tosatti:
On Mon, Dec 19, 2011 at 02:14:27AM +0100, Julian Stecklina wrote:
If the guest programs an
On 2012-01-13 12:11, Vasilis Liaskovitis wrote:
This patch series adds support for CPU _EJ0 callback in Seabios and qemu-kvm.
The first patch defines the CPU eject bitmap in Seabios and writes to it
during the callback. The second patch adds empty stub functions to qemu-kvm to
handle the
On 2012-01-13 12:11, Vasilis Liaskovitis wrote:
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
---
hw/acpi_piix4.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 8bf30dd..12eef55
On 13.01.2012, at 06:11, Paul Mackerras wrote:
On Thu, Jan 12, 2012 at 07:16:51PM +0100, Alexander Graf wrote:
While trying to run HV KVM for something useful on 970, we stumbled
over the following code path:
/* Allocate guest's hashed page table */
hpt =
On Fri, Jan 13, 2012 at 12:58:53PM +0100, Jan Kiszka wrote:
On 2012-01-13 12:11, Vasilis Liaskovitis wrote:
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
---
hw/acpi_piix4.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
On Fri, Jan 13, 2012 at 12:58:10PM +0100, Jan Kiszka wrote:
Please work against upstream (uq/master for kvm-related patches), not
qemu-kvm. It possibly makes no technical difference here, but we do not
want to let the code bases needlessly diverge again. If if does make a
difference and
On Fri, 2012-01-13 at 10:24 +0900, Takuya Yoshikawa wrote:
(2012/01/13 10:08), Davidlohr Bueso wrote:
From: Davidlohr Buesod...@gnu.org
It makes more sense to actually increment statistics for tlb flushes and
page table entry updates after such _events_ occur, instead of before.
Why?
We need the KVM_REG namespace for generic register settings now, so
let's rename the existing users to something different, enabling
us to reuse the namespace for more visible interfaces.
While at it, also move these private constants to a private header.
Signed-off-by: Alexander Graf
From: Davidlohr Bueso d...@gnu.org
Also use true instead of 1 for enabling by default.
Signed-off-by: Davidlohr Bueso d...@gnu.org
---
arch/x86/kvm/svm.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5fa553b..3c9b0dc
From: Scott Wood scottw...@freescale.com
The only place it makes sense to call this function already needs
to have preemption disabled.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c |4 +---
1 files changed, 1
From: Scott Wood scottw...@freescale.com
The hardcoded behavior prevents proper SMP support.
user space shall specify the vcpu's PIR as the vcpu id.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/booke.c |4 ++--
With hugetlbfs support emerging on e500, we should also support KVM
backing its guest memory by it.
This patch adds support for hugetlbfs into the e500 shadow mmu code.
Signed-off-by: Alexander Graf ag...@suse.de
Acked-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kvm/e500_tlb.c |
From: Bharat Bhushan r65...@freescale.com
The current implementation of mtmsr and mtmsrd are racy in that it does:
* check (int_pending == 0)
--- host sets int_pending = 1 ---
* write shared page
* done
while instead we should check for int_pending after the shared page is written.
From: Bharat Bhushan r65...@freescale.com
kvmppc_emulate_dec() uses dec_nsec of type unsigned long and does below
calculation:
dec_nsec = vcpu-arch.dec;
dec_nsec *= 1000;
This will truncate if DEC value vcpu-arch.dec is greater than
0x_/1000.
For example : For
From: Scott Wood scottw...@freescale.com
Split out the portions of tlbe_priv that should be associated with host
entries into tlbe_ref. Base victim selection on the number of hardware
entries, not guest entries.
For TLB1, where one guest entry can be mapped by multiple host entries,
we use the
From: Paul Mackerras pau...@samba.org
This relaxes the requirement that the guest memory be provided as
16MB huge pages, allowing it to be provided as normal memory, i.e.
in pages of PAGE_SIZE bytes (4k or 64k). To allow this, we index
the kvm-arch.slot_phys[] arrays with a small page index,
From: Paul Mackerras pau...@samba.org
This provides for the case where userspace maps an I/O device into the
address range of a memory slot using a VM_PFNMAP mapping. In that
case, we work out the pfn from vma-vm_pgoff, and record the cache
enable bits from vma-vm_page_prot in two low-order bits
From: Paul Mackerras pau...@samba.org
This removes the code from kvmppc_core_prepare_memory_region() that
looked up the VMA for the region being added and called hva_to_page
to get the pfns for the memory. We have no guarantee that there will
be anything mapped there at the time of the
From: Paul Mackerras pau...@samba.org
This expands the reverse mapping array to contain two links for each
HPTE which are used to link together HPTEs that correspond to the
same guest logical page. Each circular list of HPTEs is pointed to
by the rmap array entry for the guest logical page,
From: Paul Mackerras pau...@samba.org
This allocates an array for each memory slot that is added to store
the physical addresses of the pages in the slot. This array is
vmalloc'd and accessed in kvmppc_h_enter using real_vmalloc_addr().
This allows us to remove the ram_pginfo field from the
From: Scott Wood scottw...@freescale.com
Instead of keeping separate copies of struct kvm_vcpu_arch_shared (one in
the code, one in the docs) that inevitably fail to be kept in sync
(already sr[] is missing from the doc version), just point to the header
file as the source of documentation on the
From: Paul Mackerras pau...@samba.org
This moves the get/set_one_reg implementation down from powerpc.c into
booke.c, book3s_pr.c and book3s_hv.c. This avoids #ifdefs in C code,
but more importantly, it fixes a bug on Book3s HV where we were
accessing beyond the end of the kvm_vcpu struct (via
Right now we transfer a static struct every time we want to get or set
registers. Unfortunately, over time we realize that there are more of
these than we thought of before and the extensibility and flexibility of
transferring a full struct every time is limited.
So this is a new approach to the
Until now, we always set HIOR based on the PVR, but this is just wrong.
Instead, we should be setting HIOR explicitly, so user space can decide
what the initial HIOR value is - just like on real hardware.
We keep the old PVR based way around for backwards compatibility, but
once user space uses
From: Liu Yu yu@freescale.com
The existing kvm_stlb_write/kvm_gtlb_write were a poor match for
the e500/book3e MMU -- mas1 was passed as tid, mas2 was limited
to unsigned int which will be a problem on 64-bit, mas3/7 got
split up rather than treated as a single 64-bit word, etc.
We need the KVM_REG namespace for generic register settings now, so
let's rename the existing users to something different, enabling
us to reuse the namespace for more visible interfaces.
While at it, also move these private constants to a private header.
Signed-off-by: Alexander Graf
From: Sasha Levin levinsasha...@gmail.com
Currently the code kzalloc()s new VCPUs instead of using the kmem_cache
which is created when KVM is initialized.
Modify it to allocate VCPUs from that kmem_cache.
Signed-off-by: Sasha Levin levinsasha...@gmail.com
Acked-by: Paul Mackerras
From: Matt Evans m...@ozlabs.org
PPC KVM lacks these two capabilities, and as such a userland system must assume
a max of 4 VCPUs (following api.txt). With these, a userland can determine
a more realistic limit.
Signed-off-by: Matt Evans m...@ozlabs.org
Signed-off-by: Alexander Graf
From: Paul Mackerras pau...@samba.org
This uses the host view of the hardware R (referenced) bit to speed
up kvm_age_hva() and kvm_test_age_hva(). Instead of removing all
the relevant HPTEs in kvm_age_hva(), we now just reset their R bits
if set. Also, kvm_test_age_hva() now scans the relevant
From: Matt Evans m...@ozlabs.org
Fix usage of vcpu struct before check that it's actually valid.
Signed-off-by: Matt Evans m...@ozlabs.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/powerpc.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git
From: Paul Mackerras pau...@samba.org
This allows both the guest and the host to use the referenced (R) and
changed (C) bits in the guest hashed page table. The guest has a view
of R and C that is maintained in the guest_rpte field of the revmap
entry for the HPTE, and the host has a view that
From: Paul Mackerras pau...@samba.org
This reworks the implementations of the H_REMOVE and H_BULK_REMOVE
hcalls to make sure that we keep the HPTE locked and in the reverse-
mapping chain until we have finished invalidating it. Previously
we would remove it from the chain and unlock it before
From: Paul Mackerras pau...@samba.org
This changes the implementation of kvm_vm_ioctl_get_dirty_log() for
Book3s HV guests to use the hardware C (changed) bits in the guest
hashed page table. Since this makes the implementation quite different
from the Book3s PR case, this moves the existing
From: Paul Mackerras pau...@samba.org
With this, if a guest does an H_ENTER with a read/write HPTE on a page
which is currently read-only, we make the actual HPTE inserted be a
read-only version of the HPTE. We now intercept protection faults as
well as HPTE not found faults, and for a
From: Paul Mackerras pau...@samba.org
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that
From: Paul Mackerras pau...@samba.org
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables
From: Paul Mackerras pau...@samba.org
This adds an smp_wmb in kvm_mmu_notifier_invalidate_range_end() and an
smp_rmb in mmu_notifier_retry() so that mmu_notifier_retry() will give
the correct answer when called without kvm-mmu_lock being held.
PowerPC Book3S HV KVM wants to use a bitlock per
From: Paul Mackerras pau...@samba.org
This adds two new functions, kvmppc_pin_guest_page() and
kvmppc_unpin_guest_page(), and uses them to pin the guest pages where
the guest has registered areas of memory for the hypervisor to update,
(i.e. the per-cpu virtual processor areas, SLB shadow buffers
From: Paul Mackerras pau...@samba.org
At present, our implementation of H_ENTER only makes one try at locking
each slot that it looks at, and doesn't even retry the ldarx/stdcx.
atomic update sequence that it uses to attempt to lock the slot. Thus
it can return the H_PTEG_FULL error
From: Scott Wood scottw...@freescale.com
The hardware maintains a per-set next victim hint. Using this
reduces conflicts, especially on e500v2 where a single guest
TLB entry is mapped to two shadow TLB entries (user and kernel).
We want those two entries to go to different TLB ways.
sesel is
From: Paul Mackerras pau...@samba.org
This adds an array that parallels the guest hashed page table (HPT),
that is, it has one entry per HPTE, used to store the guest's view
of the second doubleword of the corresponding HPTE. The first
doubleword in the HPTE is the same as the guest's idea of
From: Liu Yu-B13201 yu@freescale.com
Currently we patch the whole code include paravirt template code.
This isn't safe for scratch area and has impact to performance.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kernel/kvm.c |
Our vcpu kick implementation differs a bit from x86 which resulted in us not
disabling preemption during the kick. Get it a bit closer to what x86 does.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/powerpc.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
From: Paul Mackerras pau...@samba.org
When commit f43fdc15fa (KVM: PPC: booke: Improve timer register
emulation) factored out some code in arch/powerpc/kvm/powerpc.c
into a new helper function, kvm_vcpu_kick(), an error crept in
which causes Book3s HV guest vcpus to stall. This fixes it.
On
As Scott put it:
If we get a signal after the check, we want to be sure that we don't
receive the reschedule IPI until after we're in the guest, so that it
will cause another signal check.
we need to have interrupts disabled from the point we do signal_check()
all the way until we actually
From: Scott Wood scottw...@freescale.com
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The
From: Scott Wood scottw...@freescale.com
The associativity, not just total size, can differ from the host
hardware.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c | 19 ++-
1 files changed, 14
From: Scott Wood scottw...@freescale.com
Decrementers are now properly driven by TCR/TSR, and the guest
has full read/write access to these registers.
The decrementer keeps ticking (and setting the TSR bit) regardless of
whether the interrupts are enabled with TCR.
The decrementer stops at
When entering the guest, we want to make sure we're not getting preempted
away, so let's disable preemption on entry, but enable it again while handling
guest exits.
Reported-by: Jörg Sommer jo...@alea.gnuu.de
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_pr.c | 13
From: Scott Wood scottw...@freescale.com
Also fix wrteei 1 paravirt to check for a pending interrupt.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kernel/kvm.c | 92 +-
Somewhere during merges we ended up from
local_irq_enable()
foo();
local_irq_disable()
to always keeping irqs enabled during that part. However, we now
have the following code:
foo();
local_irq_disable()
which disables interrupts without the surrounding code enabling them
again! So
From: Scott Wood scottw...@freescale.com
It should contain the way, not the absolute TLB0 index.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
From: Scott Wood scottw...@freescale.com
int_pending was only being lowered if a bit in pending_exceptions
was cleared during exception delivery -- but for interrupts, we clear
it during IACK/TSR emulation. This caused paravirt for enabling
MSR[EE] to be ineffective.
Signed-off-by: Scott Wood
From: Scott Wood scottw...@freescale.com
This function should be called with interrupts disabled, to avoid
a race where an exception is delivered after we check, but the
resched kick is received before we disable interrupts (and thus doesn't
actually trigger the exit code that would recheck
From: Scott Wood scottw...@freescale.com
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/api.txt | 74 +++
From: Scott Wood scottw...@freescale.com
Currently we check prior to returning from a lightweight exit,
but not prior to initial entry.
book3s already does a similar test.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/booke.c
From: Scott Wood scottw...@freescale.com
This function also updates paravirt int_pending, so rename it
to be more obvious that this is a collection of checks run prior
to (re)entering a guest.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Bharat Bhushan r65...@freescale.com
As per specification the decrementer interrupt not happen when DEC is written
with 0. Also when DEC is zero, no decrementer running. So we should not start
hrtimer for decrementer when DEC = 0.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
From: Scott Wood scottw...@freescale.com
Delay allocation of the shadow pid until we're ready to disable
preemption and write the entry.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c | 36
From: Scott Wood scottw...@freescale.com
This prevents us from inappropriately blocking in a KVM_SET_REGS
ioctl -- the MSR[WE] will take effect when the guest is next entered.
It also causes SRR1[WE] to be set when we enter the guest's interrupt
handler, which is what e500 hardware is documented
Hi Avi,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit 188fc33198ddb1469562d40de33bcc29e7e2ed5f:
Christian Borntraeger (1):
kvm-s390: provide access guest registers via kvm_run
are available in the git repository at:
When running the 64-bit Book3s PR code without CONFIG_PREEMPT_NONE, we were
doing a few things wrong, most notably access to PACA fields without making
sure that the pointers stay stable accross the access (preempt_disable()).
This patch moves to_svcpu towards a get/put model which allows us to
Introduce a memory region type that can reserve I/O space. Such regions
are useful for modeling I/O that is only handled outside of QEMU, i.e.
in the context of an accelerator like KVM.
Any access to such a region from QEMU is a bug, but could theoretically
be triggered by guest code (DMA to
Make the basic in-kernel irqchip support selectable via
-machine ...,kernel_irqchip=on. Leave it off by default until it can
fully replace user space models.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
qemu-config.c |4
qemu-options.hx |5 -
2 files changed, 8
Rename msix_supported to msi_supported and control MSI and MSI-X
activation this way. That was likely to original intention for this
flag, but MSI support came after MSI-X.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/msi.c |8
hw/msi.h |2 ++
hw/msix.c |9
As all devices undergo a reset prior to vmloa, and the reset value of
irr is 0, we do not need to do this clearing for older vmstates
explicitly. Dropping this redundant code will also make KVM integration
a bit simpler.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/ioapic.c | 12
More KVM-specific devices will come, so let's start with moving the
kvmclock into a dedicated folder.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
Makefile.target|4 ++--
configure |1 +
hw/{kvmclock.c = kvm/clock.c} |4 ++--
Split up the IOAPIC analogously to APIC and i8259. KVM will share the
IOAPICCommonState, the vmstate, reset logic and certain init parts with
the user space model.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
Makefile.target |2 +-
hw/ioapic.c | 140
Changes in v6:
- back to the roots: model irqchip variants as separate qdev devices
with a common base class
- i8259: Completely privatize PicState
- ioapic: Drop post-load irr initialization
I hope this meets all expectations now and can soon be merged.
Jan
CC: Lai Jiangshan
To enable migration between accelerated and non-accelerated APIC models,
we will need to handle the timer saving and restoring specially and can
no longer rely on the automatics of VMSTATE_TIMER. Specifically,
accelerated model will not start any QEMUTimer.
This patch therefore factors out the
This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and
extends the IRQ routing setup by the 0-2 redirection when needed.
The kvm-ioapic model has a property that allows to define its GSI base
for injecting interrupts into the kernel model. This will allow to
disentangle PIC and IOAPIC
The KVM in-kernel APIC model will reuse parts of the user space model
while providing the same frontend view to guest and most management
interfaces.
Factor out an APIC base class to encapsulate those parts that will be
shared by user space and KVM model. This class offers callback hooks for
Analogously to the APIC, we will reuse some parts of the user space
i8259 model for KVM. In this case it is a common device state, a common
vmstate, the property list, a reset core and some init bits.
This also introduces a common helper to instantiate a single i8259 chip
from the
KVM is forced to disable the IRQ0 override when we run with in-kernel
irqchip but without IRQ routing support of the kernel. Set the fwcfg
value correspondingly. This aligns us with qemu-kvm.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/pc.c|3 ++-
kvm-all.c |5 +
This introduces the alternative APIC device which makes use of KVM's
in-kernel device model. External NMI injection via LINT1 is emulated by
checking the current state of the in-kernel APIC, only injecting a NMI
into the VCPU if LINT1 is unmasked and configured to DM_NMI.
MSI is not yet
All LVTs are masked on reset, so the timer becomes ineffective. Letting
it tick nevertheless is harmless, but will at least create a spurious
trace event.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/apic.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
The in-kernel i8259 and IOAPIC backends for KVM will need this, so
encapsulate the shared bits.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/apic.c| 11 ---
hw/apic.h|1 +
trace-events |2 +-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git
On real hardware, NMI button events are injected via the LINT1 line of
the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC
LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that
should not receive them. Change the APIC emulation code to reflect this.
Based on
Use DeviceState instead of PicState in the public i8259 API. This is
cleaner and allows to reorganize the PIC data structures for KVM reuse.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/i8259.c | 15 ++-
hw/pc.h|7 +++
2 files changed, 13 insertions(+), 9
Introduce the alternative 'kvm-i8259' device model that exploits KVM
in-kernel acceleration.
The PIIX3 initialization code is furthermore extended by KVM specific
IRQ route setup. GSI injection differs in KVM mode from the user space
model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC
Add the basic infrastructure to active in-kernel irqchip support, inject
interrupts into these models, and maintain IRQ routes.
Routing is optional and depends on the host arch supporting
KVM_CAP_IRQ_ROUTING. When it's not available on x86, we looe the HPET as
we can't route GSI0 to IOAPIC pin 2.
From: Kay Sievers kay.siev...@vrfy.org
Date: Fri, 13 Jan 2012 05:19:05 +0100
On Fri, Jan 13, 2012 at 05:07, David Miller da...@davemloft.net wrote:
From: Stephen Hemminger shemmin...@vyatta.com
Date: Wed, 11 Jan 2012 21:30:38 -0800
Subject: vhost-net: add module alias (v2.1)
By adding some
On 13 January 2012 17:35, Jan Kiszka jan.kis...@siemens.com wrote:
Subject: kvm: Arm in-kernel irqchip support
I have to say I found this Subject rather confusing :-)
-- PMM
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To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
On 2012-01-13 19:49, Peter Maydell wrote:
On 13 January 2012 17:35, Jan Kiszka jan.kis...@siemens.com wrote:
Subject: kvm: Arm in-kernel irqchip support
I have to say I found this Subject rather confusing :-)
Deeply sorry, but I guess that verb predates the architecture by a few
years. ;)
Am 13.01.2012 20:04, schrieb Jan Kiszka:
On 2012-01-13 19:49, Peter Maydell wrote:
On 13 January 2012 17:35, Jan Kiszka jan.kis...@siemens.com wrote:
Subject: kvm: Arm in-kernel irqchip support
I have to say I found this Subject rather confusing :-)
Deeply sorry, but I guess that verb
On Fri, 2012-01-13 at 12:25 +0530, Shashidhar Patil wrote:
Hi Alex,
Thanks for your help. Some answers and further investigation details
inline.
On Wed, Jan 4, 2012 at 8:51 AM, Alex Williamson
alex.william...@redhat.comwrote:
On Mon, 2011-12-19 at 19:49 +0530, Shashidhar Patil wrote:
On 2012-01-04 04:21, Alex Williamson wrote:
On Mon, 2011-12-19 at 19:49 +0530, Shashidhar Patil wrote:
Hi,
I am running Ubuntu 10.10 (amd64) on a 2 socket nehalem based
server with IOH 5520. 5520 supports VTD.
I enabled DMAR with intel_iommu=on. The box has intel 82599 adapter
which
On Fri, 2012-01-13 at 22:00 +0100, Jan Kiszka wrote:
On 2012-01-04 04:21, Alex Williamson wrote:
On Mon, 2011-12-19 at 19:49 +0530, Shashidhar Patil wrote:
Hi,
I am running Ubuntu 10.10 (amd64) on a 2 socket nehalem based
server with IOH 5520. 5520 supports VTD.
I enabled DMAR
On 01/13/2012 11:35 AM, Jan Kiszka wrote:
The KVM in-kernel APIC model will reuse parts of the user space model
while providing the same frontend view to guest and most management
interfaces.
Factor out an APIC base class to encapsulate those parts that will be
shared by user space and KVM
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