https://bugzilla.kernel.org/show_bug.cgi?id=75981
Jan Kiszka jan.kis...@web.de changed:
What|Removed |Added
CC||jan.kis...@web.de
---
Hi
Please, send any topic that you are interested in covering.
- QOMifying both Memory regions and GPIOs and attaching them via QOM
links (Peter Crosthwaite)
Thanks, Juan.
Call details:
15:00 CEST
13:00 UTC
09:00 EDT
Every two weeks
If you need phone number details, contact me privately.
On 12 May 2014 10:10, Juan Quintela quint...@redhat.com wrote:
Please, send any topic that you are interested in covering.
- QOMifying both Memory regions and GPIOs and attaching them via QOM
links (Peter Crosthwaite)
Is there some further useful material on-list on this subject, or
are we
On Mon, May 12, 2014 at 7:44 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 May 2014 10:10, Juan Quintela quint...@redhat.com wrote:
Please, send any topic that you are interested in covering.
- QOMifying both Memory regions and GPIOs and attaching them via QOM
links (Peter
Il 10/05/2014 09:24, Jan Kiszka ha scritto:
From: Jan Kiszka jan.kis...@siemens.com
Regression of 346874c9: PAE is set in long mode, but that does not mean
we have valid PDPTRs.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/kvm/x86.c | 9 +
1 file changed, 5
On Fri, May 09, 2014 at 10:44:24PM +0100, James Hogan wrote:
Hi Andreas,
On 06/05/14 16:51, Andreas Herrmann wrote:
... to get rid of its function definition from archs that don't
support it.
Maybe it makes sense to put this patch before the main mips one so that
the function doesn't
On 12 May 2014 11:30, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Mon, May 12, 2014 at 7:44 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 12 May 2014 10:10, Juan Quintela quint...@redhat.com wrote:
Please, send any topic that you are interested in covering.
- QOMifying
On Fri, May 09, 2014 at 10:22:15PM +0100, James Hogan wrote:
Hi Andreas,
On 06/05/14 16:51, Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V5:
* Split the patch to two and also update commit message
Use make_dsisr instead of open coding it. This also have
the added benefit of handling alignment interrupt on additional
instructions.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/disassemble.h | 34 +
On Wed, May 07, 2014 at 07:58:30PM +0400, Sergei Shtylyov wrote:
Hello.
On 06-05-2014 19:51, Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
It is a performance enhancement. When running in a simulator, each
system call to write a character takes a lot of time.
On 12.05.14 13:34, Aneesh Kumar K.V wrote:
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Thanks, applied both to kvm-ppc-queue.
Alex
--
To
On Fri, May 09, 2014 at 10:15:29PM +0100, James Hogan wrote:
Hi Andreas,
On 06/05/14 16:51, Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
So far this was tested with host running KVM using MIPS-VZ (on Cavium
Octeon3). A paravirtualized mips kernel was used for the
On Fri, May 09, 2014 at 10:34:30PM +0100, James Hogan wrote:
Hi Andreas,
On 06/05/14 16:51, Andreas Herrmann wrote:
This is is usually 0 for most archs. On mips we have two types.
TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
Signed-off-by: Andreas Herrmann
Hi Andreas,
On 12/05/14 14:01, Andreas Herrmann wrote:
On Fri, May 09, 2014 at 10:15:29PM +0100, James Hogan wrote:
On 06/05/14 16:51, Andreas Herrmann wrote:
+static bool kvm_cpu__hypercall_write_cons(struct kvm_cpu *vcpu)
+{
+ int term = (int)vcpu-kvm_run-hypercall.args[0];
+ u64 addr
2014-05-07 11:01-0400, Waiman Long:
From: Peter Zijlstra pet...@infradead.org
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
I think there is an unwanted scenario on virtual machines:
1)
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On Mon, May 12, 2014 at 05:22:08PM +0200, Radim Krčmář wrote:
2014-05-07 11:01-0400, Waiman Long:
From: Peter Zijlstra pet...@infradead.org
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
https://bugzilla.kernel.org/show_bug.cgi?id=75981
Paolo Bonzini bonz...@gnu.org changed:
What|Removed |Added
CC||bonz...@gnu.org
---
(tl;dr: paravirtualization could be better than unfair qspinlock)
2014-05-07 11:01-0400, Waiman Long:
Locking is always an issue in a virtualized environment because of 2
different types of problems:
1) Lock holder preemption
2) Lock waiter preemption
Paravirtualized ticketlocks have a
Alex Williamson alex.william...@redhat.com :
[...]
device MSI will be blocked. The Linux driver doesn't make use of this
window, so apparently it's not required to make use of MSI-X. This
It does not really use MSI-X (no RSS).
quirk makes the device work with the Windows driver that does
The book3s_32 target can get built as module which means we don't see the
config define for it in code. Instead, check on the bool define
CONFIG_KVM_BOOK3S_32_HANDLER whenever we want to know whether we're building
for a book3s_32 host.
This fixes running book3s_32 kvm as a module for me.
Hi Paolo / Marcelo,
This is my current patch queue for 3.15. Please pull.
Alex
The following changes since commit 0f689a33ad17845363acdc6d52783befd6ad116c:
Merge branch 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux (2014-04-16 11:28:25
-0700)
are available in
From: pingf...@linux.vnet.ibm.com pingf...@linux.vnet.ibm.com
Numa fault is a method which help to achieve auto numa balancing.
When such a page fault takes place, the page fault handler will check
whether the page is placed correctly. If not, migration should be
involved to cut down the distance
On 09.05.14 13:53, Paolo Bonzini wrote:
Il 09/05/2014 04:28, Marcelo Tosatti ha scritto:
Alex,
Unability to upgrade systems is not an excuse to fix the bug in the
wrong place.
It may be an excuse to fix the bug in both places though.
The bug in the kernel should be fixed differently
From: Paul Mackerras pau...@au1.ibm.com
Testing by Michael Neuling revealed that commit e4e38121507a (KVM:
PPC: Book3S HV: Add transactional memory support) is missing the code
that saves away the checkpointed state of the guest when switching to
the host. This adds that code, which was in
Our PV guest patching code assembles chunks of instructions on the fly when it
encounters more complicated instructions to hijack. These instructions need
to live in a section that we don't mark as non-executable, as otherwise we
fault when jumping there.
Right now we put it into the .bss section
On Mon, 2014-05-12 at 22:02 +0200, Francois Romieu wrote:
Alex Williamson alex.william...@redhat.com :
[...]
device MSI will be blocked. The Linux driver doesn't make use of this
window, so apparently it's not required to make use of MSI-X. This
It does not really use MSI-X (no RSS).
On Mon, May 12, 2014 at 9:09 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 May 2014 11:30, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Mon, May 12, 2014 at 7:44 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 12 May 2014 10:10, Juan Quintela quint...@redhat.com
According PCI local bus specification, the register of Message
Control for MSI (offset: 2, length: 2) has bit#0 to enable or
disable MSI logic and it shouldn't be part contributing to the
calculation of MSI interrupt count. The patch fixes the issue.
Signed-off-by: Gavin Shan
The macro offsetofend() introduces unnecessary temporary variable
tmp. The patch avoids that and saves a bit memory in stack.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
include/linux/vfio.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/linux/vfio.h
Changelog
=
v1 - v2:
* Change the comments and commit log in PATCH[4/4] (Alex).
* Export 2 MSI relevant functions (Alex).
Gavin Shan (4):
PCI: Export MSI message relevant functions
drivers/vfio: Rework offsetofend()
drivers/vfio/pci: Fix wrong MSI interrupt count
The MSIx vector table lives in device memory, which may be cleared as
part of a backdoor device reset. This is the case on the IBM IPR HBA
when the BIST is run on the device. When assigned to a QEMU guest,
the guest driver does a pci_save_state(), issues a BIST, then does a
pci_restore_state().
The patch exports 2 MSI message relevant functions, which will be
used by VFIO PCI driver. The VFIO PCI driver would be built as
a module.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/pci/msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/msi.c
On Mon, 2014-05-12 at 14:28 -0600, Alex Williamson wrote:
On Mon, 2014-05-12 at 22:02 +0200, Francois Romieu wrote:
Alex Williamson alex.william...@redhat.com :
[...]
device MSI will be blocked. The Linux driver doesn't make use of this
window, so apparently it's not required to make
This fixes below compilation error on SOCs where CONFIG_PHYS_64BIT
is not defined:
arch/powerpc/kvm/e500_mmu_host.c: In function 'kvmppc_e500_shadow_map':
| arch/powerpc/kvm/e500_mmu_host.c:631:20: error: 'PTE_WIMGE_SHIFT' undeclared
(first use in this function)
|wimg = (*ptep
Am 13.05.2014 um 07:05 schrieb Bharat Bhushan r65...@freescale.com:
This fixes below compilation error on SOCs where CONFIG_PHYS_64BIT
is not defined:
arch/powerpc/kvm/e500_mmu_host.c: In function 'kvmppc_e500_shadow_map':
| arch/powerpc/kvm/e500_mmu_host.c:631:20: error:
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V5:
* Split the patch to two and also update commit message
Use make_dsisr instead of open coding it. This also have
the added benefit of handling alignment interrupt on additional
instructions.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/disassemble.h | 34 +
On 12.05.14 13:34, Aneesh Kumar K.V wrote:
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Thanks, applied both to kvm-ppc-queue.
Alex
--
To
Hi Paolo / Marcelo,
This is my current patch queue for 3.15. Please pull.
Alex
The following changes since commit 0f689a33ad17845363acdc6d52783befd6ad116c:
Merge branch 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux (2014-04-16 11:28:25
-0700)
are available in
From: pingf...@linux.vnet.ibm.com pingf...@linux.vnet.ibm.com
Numa fault is a method which help to achieve auto numa balancing.
When such a page fault takes place, the page fault handler will check
whether the page is placed correctly. If not, migration should be
involved to cut down the distance
Our PV guest patching code assembles chunks of instructions on the fly when it
encounters more complicated instructions to hijack. These instructions need
to live in a section that we don't mark as non-executable, as otherwise we
fault when jumping there.
Right now we put it into the .bss section
From: Paul Mackerras pau...@au1.ibm.com
Testing by Michael Neuling revealed that commit e4e38121507a (KVM:
PPC: Book3S HV: Add transactional memory support) is missing the code
that saves away the checkpointed state of the guest when switching to
the host. This adds that code, which was in
Am 13.05.2014 um 07:05 schrieb Bharat Bhushan r65...@freescale.com:
This fixes below compilation error on SOCs where CONFIG_PHYS_64BIT
is not defined:
arch/powerpc/kvm/e500_mmu_host.c: In function 'kvmppc_e500_shadow_map':
| arch/powerpc/kvm/e500_mmu_host.c:631:20: error:
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