https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #2 from Jatin Kumar jatin.iitde...@gmail.com ---
Hello Jidong, thanks for the info. I will try and let you know.
While you are at this, can you please help me another single stepping issue and
the issue is:
1. While single stepping,
https://bugzilla.kernel.org/show_bug.cgi?id=45931
Zhou, Chao chao.z...@intel.com changed:
What|Removed |Added
CC||chao.z...@intel.com
---
https://bugzilla.kernel.org/show_bug.cgi?id=75981
--- Comment #4 from Zhou, Chao chao.z...@intel.com ---
kvm.git + qemu.git: d9f89b88_e5bfd640
host kernel:3.15.0_rc1
test on Romley_EP, create a 64bit rhel6u5 guest as L2 guest, the L2 guest boots
up fine.
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Zhou, Chao chao.z...@intel.com changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugzilla.kernel.org/show_bug.cgi?id=75981
--- Comment #5 from Zhou, Chao chao.z...@intel.com ---
this commit fixed the bug:
commit d9f89b88f5102ce235b75a5907838e3c7ed84b97
Author: Jan Kiszka jan.kis...@siemens.com
Date: Sat May 10 09:24:34 2014 +0200
KVM: x86: Fix CR3 reserved bits
https://bugzilla.kernel.org/show_bug.cgi?id=75981
Zhou, Chao chao.z...@intel.com changed:
What|Removed |Added
Status|RESOLVED|VERIFIED
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You are
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
On 17.05.14 08:20, Paul Mackerras wrote:
On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf ag...@suse.de wrote:
On 19.05.14 19:03, Michael Mueller wrote:
On Mon, 19 May 2014 16:49:28 +0200
Alexander Graf ag...@suse.de wrote:
On 19.05.14 16:18, Michael Mueller wrote:
On Mon, 19 May 2014 13:48:08 +0200
Alexander Graf
On 20.05.14 12:02, Michael Mueller wrote:
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf ag...@suse.de wrote:
On 19.05.14 19:03, Michael Mueller wrote:
On Mon, 19 May 2014 16:49:28 +0200
Alexander Graf ag...@suse.de wrote:
[...]
What user and thus also user space wants depends on
https://bugzilla.kernel.org/show_bug.cgi?id=53601
Bug 53601 depends on bug 45931, which changed state.
Bug 45931 Summary: Nested Virt: VMX can't be initialized in L1 Xen (Xen on
KVM)
https://bugzilla.kernel.org/show_bug.cgi?id=45931
What|Removed |Added
https://bugzilla.kernel.org/show_bug.cgi?id=45931
Paolo Bonzini bonz...@gnu.org changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugzilla.kernel.org/show_bug.cgi?id=65561
Paolo Bonzini bonz...@gnu.org changed:
What|Removed |Added
CC||bonz...@gnu.org
---
On 19/05/14 17:53, Andreas Herrmann wrote:
Hi,
These patches contain changes that I am currently using on top of
git://github.com/penberg/linux-kvm.git (as of v3.13-rc1-1427-gd9147fb)
to run lkvm on MIPS.
The core is David's work for mips support and loading elf binaries.
I rebased his
On 19/05/14 17:53, Andreas Herrmann wrote:
This is is usually 0 for most archs. On mips we have two types.
TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
Minor thing I didn't spot with v1 (sorry).
I think this patch should probably be moved before patch 6 with the mips
part squashed
On 20.05.2014, at 11:59, Paul Mackerras pau...@samba.org wrote:
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
On 17.05.14 08:20, Paul Mackerras wrote:
On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along
Hi,
Following patches add support for paravirtualized guest on mips
(mips_paravirt). Some of the patches add basic support to run it on
octeon3.
The core of mips_paravirt is David's work.
I rebased his code, rearranged it somewhat (e.g. split it into the
current patches) and added some minor
From: David Daney david.da...@cavium.com
Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include
r4k_switch.S to pick up more FPU
From: David Daney david.da...@cavium.com
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/mm/tlbex.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
From: David Daney david.da...@cavium.com
The TLB handlers cannot handle this case, so disable it for now.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/cpu-features.h |9 -
1 file
From: David Daney david.da...@cavium.com
CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/cavium-octeon/Kconfig | 30
From: David Daney david.da...@cavium.com
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/r4kcache.h |2 ++
arch/mips/mm/c-r4k.c
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/cpu-type.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/mipsregs.h | 67 ++
1 file changed, 67 insertions(+)
diff --git
From: David Daney david.da...@cavium.com
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/mipsregs.h |5 +
1 file changed, 5
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/paravirt/setup.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/paravirt/setup.c b/arch/mips/paravirt/setup.c
index f80c3bc..6d2781c 100644
--- a/arch/mips/paravirt/setup.c
+++
From: David Daney david.da...@cavium.com
For para-virtualized guests running under KVM or other equivalent
hypervisor.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
.../asm/mach-paravirt/cpu-feature-overrides.h |
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/Kconfig|1 +
arch/mips/paravirt/Kconfig |6 ++
arch/mips/pci/Makefile |2 +-
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/configs/mips_paravirt_defconfig | 1524 +
1 file changed, 1524 insertions(+)
create mode
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/Kbuild.platforms |1 +
arch/mips/Kconfig | 19 +++
2 files changed, 20 insertions(+)
diff
Change CPU selection, enable SMP, enable almost all virtio options.
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/configs/mips_paravirt_defconfig | 69 ++---
1 file changed, 33 insertions(+), 36 deletions(-)
diff --git
The driver_override field allows us to specify the driver for a device
rather than relying on the driver to provide a positive match of the
device. This shortcuts the existing process of looking up the vendor
and device ID, adding them to the driver new_id, binding the device,
then removing the
On Tue, May 20, 2014 at 12:24:58PM +0100, James Hogan wrote:
On 19/05/14 17:53, Andreas Herrmann wrote:
This is is usually 0 for most archs. On mips we have two types.
TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
Minor thing I didn't spot with v1 (sorry).
I think this patch
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Add handlers for all the AArch64 debug registers that are accessible
from EL0 or EL1. The trapping code keeps track of the state of the
debug registers, allowing for the switch code to implement a lazy
switching strategy.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier
Enable trapping of the debug registers, preventing the guests to
mess with the host state (and allowing guests to use the debug
infrastructure as well).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/kvm/hyp.S | 8
1 file
In order to be able to use the DBG_MDSCR_* macros from the KVM code,
move the relevant definitions to the obvious include file.
Also move the debug_el enum to a portion of the file that is guarded
by #ifndef __ASSEMBLY__ in order to use that file from assembly code.
Acked-by: Will Deacon
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A57 has 6 breakpoints and 4 watchpoints, which gives us a total
of 22 registers only).
Also, we only save/restore them when MDSCR_EL1 has debug enabled,
or when we've
This patch series adds debug support, a key feature missing from the
KVM/arm64 port.
The main idea is to keep track of whether the debug registers are
dirty (changed by the guest) or not. In this case, perform the usual
save/restore dance, for one run only. It means we only have a penalty
if a
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/kvm_asm.h| 2 +-
Add handlers for all the AArch32 debug registers that are accessible
from EL0 or EL1. The code follow the same strategy as the AArch64
counterpart with regards to tracking the dirty state of the debug
registers.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier
An interesting feature of the CP14 encoding is that there is
an overlap between 32 and 64bit registers, meaning they cannot
live in the same table as we did for CP15.
Create separate tables for 64bit CP14 and CP15 registers, and
let the top level handler use the right one.
Reviewed-by: Anup
In order to allow KVM to run on Cortex-A53 implementations, wire the
minimal support required.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/cputype.h | 1 +
arch/arm64/include/uapi/asm/kvm.h| 3 ++-
arch/arm64/kvm/guest.c | 2 ++
On 05/20/2014 02:20 PM, James Hogan wrote:
I don't know what Pekka's policy is for kvm tools, but to avoid
confusion I'd like to make clear that this patchset depends on a KVM
implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into
the mainline kernel yet.
Is that something that
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #4 from Jidong Xiao jidong.x...@gmail.com ---
Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from
comment #2)
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https://bugzilla.kernel.org/show_bug.cgi?id=30402
Jidong Xiao jidong.x...@gmail.com changed:
What|Removed |Added
CC||jidong.x...@gmail.com
https://bugzilla.kernel.org/show_bug.cgi?id=30402
--- Comment #3 from Joerg Roedel j...@8bytes.org ---
(In reply to Jidong Xiao from comment #2)
Joerg, how do you know this?
Some investigation showed that this kernel uses MMX instructions to access
MMIO regions. These instructions are not
The old stats contain information not available in the tracepoints.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
diff --git a/scripts/kvm/kvm_stat b/scripts/kvm/kvm_stat
index 762544b..6ac3b21 100755
--- a/scripts/kvm/kvm_stat
+++ b/scripts/kvm/kvm_stat
@@ -493,12 +493,21 @@
On 20/05/14 18:52, Pekka Enberg wrote:
On 05/20/2014 02:20 PM, James Hogan wrote:
I don't know what Pekka's policy is for kvm tools, but to avoid
confusion I'd like to make clear that this patchset depends on a KVM
implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into
the
Hi Andreas,
On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann
Hi Andreas,
On Tuesday 20 May 2014 16:47:14 Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/configs/mips_paravirt_defconfig | 1524
On Tuesday 20 May 2014 16:47:15 Andreas Herrmann wrote:
Change CPU selection, enable SMP, enable almost all virtio options.
Looks like this should just be squashed into the previous patch if the
original defconfig was insufficient.
Cheers
James
signature.asc
Description: This is a digitally
On 05/20/2014 03:52 PM, James Hogan wrote:
Hi Andreas,
On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.
Signed-off-by: David Daney david.da...@cavium.com
On Tuesday 20 May 2014 16:47:10 Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
These look similar to the kvm_hypercall${n} functions in
From: Kim Phillips kim.phill...@freescale.com
Needed by platform device drivers, such as the vfio-platform driver
later in series, in order to bypass the existing OF, ACPI, id_table and
name string matches, and successfully be able to be bound to any
device, like so:
echo vfio-platform
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #5 from Jatin Kumar jatin.iitde...@gmail.com ---
@Paolo: Thanks for the info. That makes sense to me.
(In reply to Jidong Xiao from comment #4)
Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from
comment #2)
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #6 from Jatin Kumar jatin.iitde...@gmail.com ---
(In reply to Jatin Kumar from comment #5)
whenever I hit an out instruction, the very next instruction is not skipped
Sorry I meant 'is skipped'.
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Hi,
After download the latest qemu.git(http://git.qemu.org/?p=qemu.git;a=summary),
then compile the qemu.git, it will build fail with error
Some build log
CCtrace/generated-events.o
CCtrace/generated-tracers.o
CCutil/cutils.o
ARlibqemustub.a
lt LINK vscclient
AR
On Mon, May 19, 2014 at 06:37:24PM -0600, Alex Williamson wrote:
On Tue, 2014-05-20 at 10:22 +1000, Gavin Shan wrote:
On Mon, May 19, 2014 at 04:33:10PM -0600, Alex Williamson wrote:
On Wed, 2014-05-14 at 14:11 +1000, Gavin Shan wrote:
The patch adds new IOCTL command VFIO_EEH_INFO to VFIO
The patch introduces new flags for EEH device and PE to indicate
that the device or PE has been passed through to guest. In turn,
we will deliver EEH errors to guest for further handling, which
will be done in subsequent patches.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The patch introduces CONFIG_VFIO_PCI_EEH for more IOCTL commands
on VFIO PCI device support EEH funtionality for PCI devices that
are passed through from host to guest.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/vfio/pci/Kconfig | 6 ++
1 file changed, 6 insertions(+)
The patch adds new IOCTL command VFIO_EEH_OP to VFIO PCI device
to support EEH functionality for PCI devices, which have been
passed from host to guest via VFIO.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/Makefile | 1 +
If we detects frozen state on PE that has been passed to guest, we
needn't handle it. Instead, we rely on the guest to detect and recover
it. The patch avoid EEH event on the frozen passed PE so that the guest
can have chance to handle that.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The series of patches intends to support EEH for PCI devices, which are
passed through to PowerKVM based guest via VFIO. The implementation is
straightforward based on the issues or problems we have to resolve to
support EEH for PowerKVM based guest.
- Emulation for EEH RTAS requests. All EEH
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
On 17.05.14 08:20, Paul Mackerras wrote:
On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of
On 20.05.14 10:28, Gavin Shan wrote:
On Mon, May 19, 2014 at 06:37:24PM -0600, Alex Williamson wrote:
On Tue, 2014-05-20 at 10:22 +1000, Gavin Shan wrote:
On Mon, May 19, 2014 at 04:33:10PM -0600, Alex Williamson wrote:
On Wed, 2014-05-14 at 14:11 +1000, Gavin Shan wrote:
The patch adds new
On 20.05.14 10:30, Gavin Shan wrote:
The patch adds new IOCTL command VFIO_EEH_OP to VFIO PCI device
to support EEH functionality for PCI devices, which have been
passed from host to guest via VFIO.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
On 20.05.14 10:30, Gavin Shan wrote:
If we detects frozen state on PE that has been passed to guest, we
needn't handle it. Instead, we rely on the guest to detect and recover
it. The patch avoid EEH event on the frozen passed PE so that the guest
can have chance to handle that.
Signed-off-by:
On Tue, May 20, 2014 at 01:28:40PM +0200, Alexander Graf wrote:
On 20.05.14 13:21, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
The patch adds new IOCTL command VFIO_EEH_OP to VFIO PCI device
to support EEH functionality for PCI devices, which have been
passed from host to guest
On 20.05.14 13:40, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:28:40PM +0200, Alexander Graf wrote:
On 20.05.14 13:21, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
The patch adds new IOCTL command VFIO_EEH_OP to VFIO PCI device
to support EEH functionality for PCI devices,
On 20.05.2014, at 11:59, Paul Mackerras pau...@samba.org wrote:
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
On 17.05.14 08:20, Paul Mackerras wrote:
On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along
On Tue, May 20, 2014 at 01:25:11PM +0200, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
If we detects frozen state on PE that has been passed to guest, we
needn't handle it. Instead, we rely on the guest to detect and recover
it. The patch avoid EEH event on the frozen passed PE so
On 20.05.14 13:56, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:25:11PM +0200, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
If we detects frozen state on PE that has been passed to guest, we
needn't handle it. Instead, we rely on the guest to detect and recover
it. The patch
On Tue, May 20, 2014 at 01:44:21PM +0200, Alexander Graf wrote:
On 20.05.14 13:40, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:28:40PM +0200, Alexander Graf wrote:
On 20.05.14 13:21, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
The patch adds new IOCTL command VFIO_EEH_OP to VFIO
On 20.05.14 14:21, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:44:21PM +0200, Alexander Graf wrote:
On 20.05.14 13:40, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:28:40PM +0200, Alexander Graf wrote:
On 20.05.14 13:21, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
The patch
On Tue, May 20, 2014 at 02:25:45PM +0200, Alexander Graf wrote:
On 20.05.14 14:21, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:44:21PM +0200, Alexander Graf wrote:
On 20.05.14 13:40, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:28:40PM +0200, Alexander Graf wrote:
On 20.05.14 13:21, Alexander
On Tue, May 20, 2014 at 02:14:56PM +0200, Alexander Graf wrote:
On 20.05.14 13:56, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:25:11PM +0200, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
If we detects frozen state on PE that has been passed to guest, we
needn't handle it. Instead,
On 20.05.14 14:45, Gavin Shan wrote:
On Tue, May 20, 2014 at 02:14:56PM +0200, Alexander Graf wrote:
On 20.05.14 13:56, Gavin Shan wrote:
On Tue, May 20, 2014 at 01:25:11PM +0200, Alexander Graf wrote:
On 20.05.14 10:30, Gavin Shan wrote:
If we detects frozen state on PE that has been
On Tue, 2014-05-20 at 21:56 +1000, Gavin Shan wrote:
.../...
I think what you want is an irqfd that the in-kernel eeh code
notifies when it sees a failure. When such an fd exists, the kernel
skips its own error handling.
Yeah, it's a good idea and something for me to improve in phase
On Tue, 2014-05-20 at 15:49 +0200, Alexander Graf wrote:
Instead of
if (passed_flag)
return;
you would do
if (trigger_irqfd) {
trigger_irqfd();
return;
}
which would be a much nicer, generic interface.
But that's not how PAPR works.
Cheers,
Ben.
--
To
On Tue, 2014-05-20 at 15:49 +0200, Alexander Graf wrote:
So how about we just implement this whole thing properly as irqfd?
Whether QEMU can actually do anything with the interrupt is a different
question - we can leave it be for now. But we could model all the code
with the assumption that
On Tue, 2014-05-20 at 14:25 +0200, Alexander Graf wrote:
- Move eeh-vfio.c to drivers/vfio/pci/
- From eeh-vfio.c, dereference arch/powerpc/kernel/eeh.c::eeh_ops,
which
is arch/powerpc/plaforms/powernv/eeh-powernv.c::powernv_eeh_ops.
Call
Hrm, I think it'd be nicer to just export
On Tue, 2014-05-20 at 22:39 +1000, Gavin Shan wrote:
Yeah. How about this? :-)
- Move eeh-vfio.c to drivers/vfio/pci/
- From eeh-vfio.c, dereference arch/powerpc/kernel/eeh.c::eeh_ops, which
is arch/powerpc/plaforms/powernv/eeh-powernv.c::powernv_eeh_ops. Call
Hrm, I think it'd be
On Wed, May 21, 2014 at 10:23:52AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-20 at 22:39 +1000, Gavin Shan wrote:
Yeah. How about this? :-)
- Move eeh-vfio.c to drivers/vfio/pci/
- From eeh-vfio.c, dereference arch/powerpc/kernel/eeh.c::eeh_ops, which
is
On Wed, May 21, 2014 at 10:12:11AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-20 at 21:56 +1000, Gavin Shan wrote:
.../...
I think what you want is an irqfd that the in-kernel eeh code
notifies when it sees a failure. When such an fd exists, the kernel
skips its own error handling.
The series of patches intends to support EEH for PCI devices, which are
passed through to PowerKVM based guest via VFIO. The implementation is
straightforward based on the issues or problems we have to resolve to
support EEH for PowerKVM based guest.
- Emulation for EEH RTAS requests. All EEH
The patch adds new IOCTL command VFIO_EEH_OP to VFIO PCI device
to support EEH functionality for PCI devices, which have been
passed from host to guest via VFIO.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
Documentation/vfio.txt | 6 +-
arch/powerpc/include/asm/eeh.h | 10
The patch introduces new flags for EEH device and PE to indicate
that the device or PE has been passed through to guest. In turn,
we will deliver EEH errors to guest for further handling, which
will be done in subsequent patches.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The patch introduces CONFIG_VFIO_PCI_EEH for more IOCTL commands
on VFIO PCI device support EEH funtionality for PCI devices that
are passed through from host to guest.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/vfio/pci/Kconfig | 6 ++
1 file changed, 6 insertions(+)
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