On 2014-06-13 10:45, Paolo Bonzini wrote:
Il 13/06/2014 08:23, Jan Kiszka ha scritto:
That would preserve zero-copy capabilities (as long as you can work
against the shared mem directly, e.g. doing DMA from a physical NIC or
storage device into it) and keep the hypervisor out of the loop.
From: Waiman Long waiman.l...@hp.com
This patch extracts the logic for the exchange of new and previous tail
code words into a new xchg_tail() function which can be optimized in a
later patch.
Signed-off-by: Waiman Long waiman.l...@hp.com
Signed-off-by: Peter Zijlstra pet...@infradead.org
---
From: Waiman Long waiman.l...@hp.com
This patch makes the necessary changes at the x86 architecture
specific layer to enable the use of queue spinlock for x86-64. As
x86-32 machines are typically not multi-socket. The benefit of queue
spinlock may not be apparent. So queue spinlock is not
The current emulation of bit operations ignores the offset from the destination
on 64-bit target memory operands. This patch fixes this behavior.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/emulate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Nadav Amit nadav.a...@gmail.com
When the guest sets DR6 and DR7, KVM asserts the high 32-bits are clear, and
otherwise injects a #GP exception. This exception should only be injected only
if running in long-mode.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/x86.c |
From: Waiman Long waiman.l...@hp.com
This patch renames the paravirt_ticketlocks_enabled static key to a
more generic paravirt_spinlocks_enabled name.
Signed-off-by: Waiman Long waiman.l...@hp.com
Signed-off-by: Peter Zijlstra pet...@infradead.org
---
arch/x86/include/asm/spinlock.h |4
Signed-off-by: Peter Zijlstra pet...@infradead.org
---
arch/x86/kernel/kvm.c | 58 ++
kernel/Kconfig.locks |2 -
2 files changed, 59 insertions(+), 1 deletion(-)
Index: linux-2.6/arch/x86/kernel/kvm.c
On long-mode the current NOP (0x90) emulation still writes back to RAX. As a
result, EAX is zero-extended and the high 32-bits of RAX are cleared.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/emulate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
On Thu, Jun 12, 2014 at 04:54:52PM -0400, Waiman Long wrote:
If two tasks see the pending bit goes away and try to grab it with cmpxchg,
there is no way we can avoid the contention. However, if some how the
pending bit holder get the lock and another task set the pending bit before
the current
The emulator does not emulate the xadd instruction correctly if the two
operands are the same. In this (unlikely) situation the result should be the
sum of X and X (2X) when it is currently X. The solution is to first perform
writeback to the source, before writing to the destination. The only
On Thu, Jun 12, 2014 at 05:08:28PM -0400, Waiman Long wrote:
Native performance is king, try your very utmost bestest to preserve
that, paravirt is a distant second and nobody sane should care about the
virt case at all.
The patch won't affect native performance unless the kernel is built
Even if the condition of cmov is not satisfied, bits[63:32] should be cleared.
This is clearly stated in Intel's CMOVcc documentation. The solution is to
reassign the destination onto itself if the condition is unsatisfied. For that
matter the original destination value needs to be read.
This patch-set resolves several emulator bugs. Each fix is independent of the
others. The DR6/7 bug can occur during DR-access exit (regardless to
unrestricted mode, MMIO and SPT).
Thanks for reviewing the patches,
Nadav
Nadav Amit (6):
KVM: x86: bit-ops emulation ignores offset on 64-bit
Return unhandlable error on inter-privilage level ret instruction. This is
since the current emulation does not check the privilage level correctly when
loading the CS, and does not pop RSP/SS as needed.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/emulate.c | 4
1
XXX: merge into the pending bit patch..
It is possible so observe the pending bit without the locked bit when
the last owner has just released but the pending owner has not yet
taken ownership.
In this case we would normally queue -- because the pending bit is
already taken. However, in this
When we detect a hypervisor (!paravirt, see later patches), revert to
a simple test-and-set lock to avoid the horrors of queue preemption.
Signed-off-by: Peter Zijlstra pet...@infradead.org
---
arch/x86/include/asm/qspinlock.h | 14 ++
include/asm-generic/qspinlock.h |7
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
Signed-off-by: Peter Zijlstra pet...@infradead.org
---
include/asm-generic/qspinlock_types.h | 12 ++-
kernel/locking/qspinlock.c|
Since Waiman seems incapable of doing simple things; here's my take on the
paravirt crap.
The first few patches are taken from Waiman's latest series, but the virt
support is completely new. Its primary aim is to not mess up the native code.
I've not stress tested it, but the virt and paravirt
On Thu, Jun 12, 2014 at 04:48:41PM -0400, Waiman Long wrote:
I don't have a good understanding of the kernel alternatives mechanism.
I didn't either; I do now, cost me a whole day reading up on
alternative/paravirt code patching.
See the patches I just send out; I got the 'native' case with
Add minimal paravirt support.
The code aims for minimal impact on the native case.
On the lock side we add one jump label (asm_goto) and 4 paravirt
callee saved calls that default to NOPs. The only effects are the
extra NOPs and some pointless MOVs to accomodate the calling
convention. No
From: Waiman Long waiman.l...@hp.com
Currently, atomic_cmpxchg() is used to get the lock. However, this is
not really necessary if there is more than one task in the queue and
the queue head don't need to reset the queue code word. For that case,
a simple write to set the lock bit is enough as
From: Peter Zijlstra pet...@infradead.org
When we allow for a max NR_CPUS 2^14 we can optimize the pending
wait-acquire and the xchg_tail() operations.
By growing the pending bit to a byte, we reduce the tail to 16bit.
This means we can use xchg16 for the tail part and do away with all
the
From: Waiman Long waiman.l...@hp.com
This patch introduces a new generic queue spinlock implementation that
can serve as an alternative to the default ticket spinlock. Compared
with the ticket spinlock, this queue spinlock should be almost as fair
as the ticket spinlock. It has about the same
From: Jan Kiszka jan.kis...@siemens.com
Many real CPUs get this wrong as well, but ours is totally off: bits 9:1
define the highest index value.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/kvm/vmx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Nothing critical, but it further improves emulation accuracy,
specifically helpful when analyzing guest bugs...
Corresponding kvm-unit-tests will be provided.
Jan Kiszka (5):
KVM: nVMX: Fix returned value of MSR_IA32_VMX_PROCBASED_CTLS
KVM: nVMX: Advertise support for
From: Jan Kiszka jan.kis...@siemens.com
Allow L1 to leak its debug controls into L2, i.e. permit cleared
VM_{ENTRY_LOAD,EXIT_SAVE}_DEBUG_CONTROLS. This requires to manually
transfer the state of DR7 and IA32_DEBUGCTLMSR from L1 into L2 as both
run on different VMCS.
Signed-off-by: Jan Kiszka
From: Jan Kiszka jan.kis...@siemens.com
We already had this control enabled by exposing the broken
MSR_IA32_VMX_PROCBASED_CTLS value. This now advertises our capability by
clearing the right bits in MSR_IA32_VMX_TRUE_PROCBASED_CTLS. We also
have to ensure to test the right value on L2 entry.
From: Jan Kiszka jan.kis...@siemens.com
We already implemented them but failed to advertise them. Currently they
all return the identical values to the capability MSRs they are
augmenting. So there is no change in exposed features yet.
Drop related comments at this chance that are partially
From: Jan Kiszka jan.kis...@siemens.com
SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set. Fixing this
temporarily revokes the ability of L1 to control CR3 interceptions.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/include/asm/vmx.h | 3 +++
arch/x86/kvm/vmx.c | 5
From: Jan Kiszka jan.kis...@siemens.com
Need to fix FIELD_* constants for this to make the exit qualification
check work.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.h | 2 ++
x86/vmx_tests.c | 32 +---
2 files changed, 31 insertions(+), 3
From: Jan Kiszka jan.kis...@siemens.com
Consistently make sure we are not affected by any compiler reordering
when evaluating the current stage.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx_tests.c | 80 -
1 file changed,
From: Jan Kiszka jan.kis...@siemens.com
This particularly checks the case when debug controls are not to be
loaded/saved on host-guest transitions.
We have to fake results related to IA32_DEBUGCTL as support for this MSR
is missing KVM. The test already contains all bits required once KVM
adds
From: Jan Kiszka jan.kis...@siemens.com
Extend the instruction interception test to also check for
interception-free execution.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx_tests.c | 121 +---
1 file changed, 72 insertions(+),
From: Jan Kiszka jan.kis...@siemens.com
Check for required-0 or required-1 bits as well as known field value
restrictions. Also check the consistency between VMX_*_CTLS and
VMX_TRUE_*_CTLS and between CR0/4_FIXED0 and CR0/4_FIXED1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.c
The tests corresponding to (and going beyond) the issues fixed in
http://thread.gmane.org/gmane.comp.emulators.kvm.devel/123282
Jan Kiszka (5):
VMX: Add tests for CR3 and CR8 interception
VMX: Only use get_stage accessor
VMX: Test both interception and execution of instructions
VMX:
With guests supporting Multiple page size per segment (MPSS),
hpte_page_size returns the actual page size used. Add a new function to
return base page size and use that to compare against the the page size
calculated from SLB. Without this patch a hpte lookup can fail since
we are comparing wrong
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Alexander Graf ag...@suse.de writes:
So far we've been able to successfully run HV KVM on big endian hosts, but
once you dive into little endian land things start to fall apart.
This patch set enables HV KVM for little endian hosts. This should be the
final piece left missing to get little
On Thu, Jun 12, 2014 at 11:53:16AM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Michal Nazarewicz min...@mina86.com wrote:
I used “function(arg1, arg2, …)” at the *beginning* of functions when
the arguments passed to the function were included in the message. In
all other cases I
On Thu, Jun 12, 2014 at 12:02:38PM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Joonsoo Kim iamjoonsoo@lge.com wrote:
ppc kvm's cma area management needs alignment constraint on
I've noticed it earlier and cannot seem to get to terms with this. It
should IMO be PPC, KVM and CMA
On Thu, Jun 12, 2014 at 12:19:54PM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Joonsoo Kim iamjoonsoo@lge.com wrote:
ppc kvm's cma region management requires arbitrary bitmap granularity,
since they want to reserve very large memory and manage this region
with bitmap that one
On Thu, Jun 12, 2014 at 02:37:43PM +0900, Minchan Kim wrote:
On Thu, Jun 12, 2014 at 12:21:40PM +0900, Joonsoo Kim wrote:
To prepare future generalization work on cma area management code,
we need to separate core cma management codes from DMA APIs.
We will extend these core functions to
On Sat, Jun 14, 2014 at 03:46:44PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they
On Sat, Jun 14, 2014 at 03:35:33PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Acked-by: Michal Nazarewicz min...@mina86.com
On Sat, Jun 14, 2014 at 12:55:39PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they
On Sat, Jun 14, 2014 at 02:23:59PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Acked-by: Michal Nazarewicz min...@mina86.com
Conventionally, we put output param to the end of param list
and put the 'base' ahead of 'size', but cma_declare_contiguous()
doesn't look like that, so change it.
Additionally, move down cma_areas reference code to the position
where it is really needed.
v3: put 'base' ahead of 'size' (Minchan)
To prepare future generalization work on CMA area management code,
we need to separate core CMA management codes from DMA APIs.
We will extend these core functions to cover requirements of
PPC KVM's CMA area management functionality in following patches.
This separation helps us not to touch DMA
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
v3: add zeroing to CMA region (Aneesh)
fix compile error (Aneesh)
move VM_BUG_ON() to kvm_alloc_hpt() in book3s_hv_builtin.c (Aneesh)
Acked-by: Michal
We can remove one call sites for clear_cma_bitmap() if we first
call it before checking error number.
Acked-by: Minchan Kim minc...@kernel.org
Reviewed-by: Michal Nazarewicz min...@mina86.com
Reviewed-by: Zhang Yanfei zhangyan...@cn.fujitsu.com
Reviewed-by: Aneesh Kumar K.V
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
From my guess, it is caused by some needs on bitmap management. KVM side
wants to maintain
We should free memory for bitmap when we find zone mis-match,
otherwise this memory will leak.
Additionally, I copy code comment from PPC KVM's CMA code to inform
why we need to check zone mis-match.
* Note
Minchan suggested to add a tag for the stable, but, I don't do it,
because I found this
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
From my guess, it is caused by some needs on bitmap management. Kvm side
wants to maintain
We don't need explicit 'CMA:' prefix, since we already define prefix
'cma:' in pr_fmt. So remove it.
Acked-by: Michal Nazarewicz min...@mina86.com
Reviewed-by: Zhang Yanfei zhangyan...@cn.fujitsu.com
Signed-off-by: Joonsoo Kim iamjoonsoo@lge.com
diff --git a/mm/cma.c b/mm/cma.c
index
PPC KVM's CMA area management requires arbitrary bitmap granularity,
since they want to reserve very large memory and manage this region
with bitmap that one bit for several pages to reduce management overheads.
So support arbitrary bitmap granularity for following generalization.
v3: use
With guests supporting Multiple page size per segment (MPSS),
hpte_page_size returns the actual page size used. Add a new function to
return base page size and use that to compare against the the page size
calculated from SLB. Without this patch a hpte lookup can fail since
we are comparing wrong
Alexander Graf ag...@suse.de writes:
So far we've been able to successfully run HV KVM on big endian hosts, but
once you dive into little endian land things start to fall apart.
This patch set enables HV KVM for little endian hosts. This should be the
final piece left missing to get little
On Thu, Jun 12, 2014 at 11:53:16AM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Michal Nazarewicz min...@mina86.com wrote:
I used “function(arg1, arg2, …)” at the *beginning* of functions when
the arguments passed to the function were included in the message. In
all other cases I
On Thu, Jun 12, 2014 at 12:02:38PM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Joonsoo Kim iamjoonsoo@lge.com wrote:
ppc kvm's cma area management needs alignment constraint on
I've noticed it earlier and cannot seem to get to terms with this. It
should IMO be PPC, KVM and CMA
On Thu, Jun 12, 2014 at 12:19:54PM +0200, Michal Nazarewicz wrote:
On Thu, Jun 12 2014, Joonsoo Kim iamjoonsoo@lge.com wrote:
ppc kvm's cma region management requires arbitrary bitmap granularity,
since they want to reserve very large memory and manage this region
with bitmap that one
On Thu, Jun 12, 2014 at 02:37:43PM +0900, Minchan Kim wrote:
On Thu, Jun 12, 2014 at 12:21:40PM +0900, Joonsoo Kim wrote:
To prepare future generalization work on cma area management code,
we need to separate core cma management codes from DMA APIs.
We will extend these core functions to
On Sat, Jun 14, 2014 at 03:46:44PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they
On Sat, Jun 14, 2014 at 03:35:33PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Acked-by: Michal Nazarewicz min...@mina86.com
On Sat, Jun 14, 2014 at 12:55:39PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they
On Sat, Jun 14, 2014 at 02:23:59PM +0530, Aneesh Kumar K.V wrote:
Joonsoo Kim iamjoonsoo@lge.com writes:
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Acked-by: Michal Nazarewicz min...@mina86.com
We should free memory for bitmap when we find zone mis-match,
otherwise this memory will leak.
Additionally, I copy code comment from PPC KVM's CMA code to inform
why we need to check zone mis-match.
* Note
Minchan suggested to add a tag for the stable, but, I don't do it,
because I found this
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
v3: add zeroing to CMA region (Aneesh)
fix compile error (Aneesh)
move VM_BUG_ON() to kvm_alloc_hpt() in book3s_hv_builtin.c (Aneesh)
Acked-by: Michal
PPC KVM's CMA area management requires arbitrary bitmap granularity,
since they want to reserve very large memory and manage this region
with bitmap that one bit for several pages to reduce management overheads.
So support arbitrary bitmap granularity for following generalization.
v3: use
To prepare future generalization work on CMA area management code,
we need to separate core CMA management codes from DMA APIs.
We will extend these core functions to cover requirements of
PPC KVM's CMA area management functionality in following patches.
This separation helps us not to touch DMA
Conventionally, we put output param to the end of param list
and put the 'base' ahead of 'size', but cma_declare_contiguous()
doesn't look like that, so change it.
Additionally, move down cma_areas reference code to the position
where it is really needed.
v3: put 'base' ahead of 'size' (Minchan)
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
From my guess, it is caused by some needs on bitmap management. KVM side
wants to maintain
We don't need explicit 'CMA:' prefix, since we already define prefix
'cma:' in pr_fmt. So remove it.
Acked-by: Michal Nazarewicz min...@mina86.com
Reviewed-by: Zhang Yanfei zhangyan...@cn.fujitsu.com
Signed-off-by: Joonsoo Kim iamjoonsoo@lge.com
diff --git a/mm/cma.c b/mm/cma.c
index
PPC KVM's CMA area management needs alignment constraint on
CMA region. So support it to prepare generalization of CMA area
management functionality.
Additionally, add some comments which tell us why alignment
constraint is needed on CMA region.
v3: fix wrongly spelled word,
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