- Messaggio originale -
Da: Aurelien Jarno aurel...@aurel32.net
A: Sanjay Lal sanj...@kymasys.com
Cc: James Hogan james.ho...@imgtec.com, qemu-de...@nongnu.org, Peter
Maydell peter.mayd...@linaro.org,
kvm@vger.kernel.org, Gleb Natapov g...@redhat.com, Paolo Bonzini
On 20/06/14 02:39, Chalamarla, Tirumalesh wrote:
Hi Tirumalesh,
Is there a public repo where we can get this patches from easily.
Indeed, many thanks to Marc who hosts now my patches on his kernel.org
repo. Simply checkout the gicv3/kvm-guest branch from
On 19/06/14 22:15, Chalamarla, Tirumalesh wrote:
-Original Message-
From: kvmarm-boun...@lists.cs.columbia.edu
[mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Andre Przywara
Sent: Thursday, June 19, 2014 2:46 AM
To: linux-arm-ker...@lists.infradead.org;
On 19/06/14 22:43, Chalamarla, Tirumalesh wrote:
-Original Message-
From: kvmarm-boun...@lists.cs.columbia.edu
[mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Andre Przywara
Sent: Thursday, June 19, 2014 2:46 AM
To: linux-arm-ker...@lists.infradead.org;
Hi,
On 20/06/14 07:07, Paolo Bonzini wrote:
- Messaggio originale -
Da: Aurelien Jarno aurel...@aurel32.net
A: Sanjay Lal sanj...@kymasys.com
Cc: James Hogan james.ho...@imgtec.com, qemu-de...@nongnu.org, Peter
Maydell peter.mayd...@linaro.org,
kvm@vger.kernel.org, Gleb Natapov
On 20/06/14 09:34, Andre Przywara wrote:
On 19/06/14 22:15, Chalamarla, Tirumalesh wrote:
-Original Message-
From: kvmarm-boun...@lists.cs.columbia.edu
[mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Andre Przywara
Sent: Thursday, June 19, 2014 2:46 AM
To:
On Thu, Jun 19, 2014 at 07:40:02PM +0100, Marc Zyngier wrote:
Hi Mark,
On 19/06/14 15:01, Mark Rutland wrote:
Hi Marc,
On Thu, Jun 19, 2014 at 10:19:27AM +0100, Marc Zyngier wrote:
Linux has some requirements that must be satisfied in order to boot
on a system built with a GICv3.
On Fri, Jun 20, 2014 at 02:07:05AM -0400, Paolo Bonzini wrote:
- Messaggio originale -
Da: Aurelien Jarno aurel...@aurel32.net
A: Sanjay Lal sanj...@kymasys.com
Cc: James Hogan james.ho...@imgtec.com, qemu-de...@nongnu.org, Peter
Maydell peter.mayd...@linaro.org,
On 19/06/14 22:47, Aurelien Jarno wrote:
On Thu, Jun 19, 2014 at 12:34:24PM -0700, Sanjay Lal wrote:
On Jun 19, 2014, at 9:27 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On Tue, Jun 17, 2014 at 11:10:35PM +0100, James Hogan wrote:
In KVM mode the bootrom is loaded and executed from the
Hi Marc,
I have some minor comments below.
On Thu, Jun 19, 2014 at 10:19:25AM +0100, Marc Zyngier wrote:
The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System
On Thu, Jun 19, 2014 at 04:22:57PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 10:21:16AM +0300, Gleb Natapov wrote:
On Wed, Jun 18, 2014 at 08:12:05PM -0300, mtosa...@redhat.com wrote:
Allow vcpus to pin spte translations by:
1) Creating a per-vcpu list of pinned ranges.
On Thu, Jun 19, 2014 at 03:28:25PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 09:48:50AM +0300, Gleb Natapov wrote:
On Wed, Jun 18, 2014 at 08:12:06PM -0300, mtosa...@redhat.com wrote:
Request KVM_REQ_MMU_RELOAD when deleting sptes from MMU notifiers.
Keep pinned sptes
Hi Mark,
On 20/06/14 11:02, Mark Rutland wrote:
Hi Marc,
I have some minor comments below.
On Thu, Jun 19, 2014 at 10:19:25AM +0100, Marc Zyngier wrote:
The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
-
Il 20/06/2014 11:10, Aurelien Jarno ha scritto:
My idea was to add a machines-specific option umkernel=on, and require it
in order to run KVM. Later we can add umkernel=on support for TCG as well,
while umkernel=off with KVM requires virtualization extensions.
The same option can disable
On Thu, Jun 19, 2014 at 03:40:31PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 11:17:19AM +0300, Gleb Natapov wrote:
On Wed, Jun 18, 2014 at 08:12:07PM -0300, mtosa...@redhat.com wrote:
Reload remote vcpus MMU from GET_DIRTY_LOG codepath, before
deleting a pinned spte.
On 06/19/2014 06:52 PM, Kirill A. Shutemov wrote:
http://marc.info/?l=linux-kernelm=140319579508104w=2
Yes, those symptoms look very familiar. The patch should really go in stable
3.15.y.
Thanks.
Ortwin
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Il 20/06/2014 11:25, James Hogan ha scritto:
On 19/06/14 22:47, Aurelien Jarno wrote:
On Thu, Jun 19, 2014 at 12:34:24PM -0700, Sanjay Lal wrote:
On Jun 19, 2014, at 9:27 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On Tue, Jun 17, 2014 at 11:10:35PM +0100, James Hogan wrote:
In KVM mode
On Thu, Jun 19, 2014 at 04:00:24PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 12:20:32PM +0300, Gleb Natapov wrote:
CCing Marcelo,
On Wed, Jun 18, 2014 at 02:50:44PM +0800, Tang Chen wrote:
Hi Gleb,
Thanks for the quick reply. Please see below.
On 06/18/2014
On Fri, Jun 20, 2014 at 12:38:30PM +0200, Paolo Bonzini wrote:
Il 20/06/2014 11:10, Aurelien Jarno ha scritto:
My idea was to add a machines-specific option umkernel=on, and require it
in order to run KVM. Later we can add umkernel=on support for TCG as well,
while umkernel=off with KVM
On Fri, Jun 20, 2014 at 10:25:24AM +0100, James Hogan wrote:
On 19/06/14 22:47, Aurelien Jarno wrote:
On Thu, Jun 19, 2014 at 12:34:24PM -0700, Sanjay Lal wrote:
On Jun 19, 2014, at 9:27 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On Tue, Jun 17, 2014 at 11:10:35PM +0100, James Hogan
On 20/06/14 12:19, Aurelien Jarno wrote:
On Fri, Jun 20, 2014 at 12:38:30PM +0200, Paolo Bonzini wrote:
Il 20/06/2014 11:10, Aurelien Jarno ha scritto:
My idea was to add a machines-specific option umkernel=on, and require it
in order to run KVM. Later we can add umkernel=on support for TCG
This patch enables irqfd and irq routing on ARM.
It turns CONFIG_HAVE_KVM_EVENTFD and CONFIG_HAVE_KVM_IRQ_ROUTING on.
irqfd framework enables to inject a virtual IRQ into a guest upon an
eventfd trigger.
1) user-side first needs to setup a GSI routing table using
KVM_SET_GSI_ROUTING ioctl. A
Hello,
(as suggested by Paolo, ccing Claudio and kvm mailing list)
Here is a patchset containing an update on ivshmem specs documentation and
importing ivshmem server and client tools.
These tools have been written from scratch and are not related to what is
available in nahanni repository.
I
When using ivshmem devices, notifications between guests can be sent as
interrupts using a ivshmem-server (typical use described in documentation).
The client is provided as a debug tool.
Signed-off-by: David Marchand david.march...@6wind.com
---
contrib/ivshmem-client/Makefile | 26 ++
Add some notes on the parts needed to use ivshmem devices: more specifically,
explain the purpose of an ivshmem server and the basic concept to use the
ivshmem devices in guests.
Signed-off-by: David Marchand david.march...@6wind.com
---
docs/specs/ivshmem_device_spec.txt | 41
On Fri, Jun 20, 2014 at 02:15:10PM +0300, Gleb Natapov wrote:
On Thu, Jun 19, 2014 at 04:00:24PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 12:20:32PM +0300, Gleb Natapov wrote:
CCing Marcelo,
On Wed, Jun 18, 2014 at 02:50:44PM +0800, Tang Chen wrote:
Hi Gleb,
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
In order to be able to use the DBG_MDSCR_* macros from the KVM code,
move the relevant definitions to the obvious include file.
Also move the debug_el enum to a portion of the file that is guarded
by #ifndef __ASSEMBLY__ in order to use that file from assembly code.
Acked-by: Will Deacon
This patch series adds debug support, a key feature missing from the
KVM/arm64 port.
The main idea is to keep track of whether the debug registers are
dirty (changed by the guest) or not. In this case, perform the usual
save/restore dance, for one run only. It means we only have a penalty
if a
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc
Add handlers for all the AArch32 debug registers that are accessible
from EL0 or EL1. The code follow the same strategy as the AArch64
counterpart with regards to tracking the dirty state of the debug
registers.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A57 has 6 breakpoints and 4 watchpoints, which gives us a total
of 22 registers only).
Also, we only save/restore them when MDSCR_EL1 has debug enabled,
or when we've
Enable trapping of the debug registers, preventing the guests to
mess with the host state (and allowing guests to use the debug
infrastructure as well).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier
Add handlers for all the AArch64 debug registers that are accessible
from EL0 or EL1. The trapping code keeps track of the state of the
debug registers, allowing for the switch code to implement a lazy
switching strategy.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Marc Zyngier
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
An interesting feature of the CP14 encoding is that there is
an overlap between 32 and 64bit registers, meaning they cannot
live in the same table as we did for CP15.
Create separate tables for 64bit CP14 and CP15 registers, and
let the top level handler use the right one.
Reviewed-by: Anup
On Sun, Jun 15, 2014 at 02:47:07PM +0200, Peter Zijlstra wrote:
Add minimal paravirt support.
The code aims for minimal impact on the native case.
Woot!
On the lock side we add one jump label (asm_goto) and 4 paravirt
callee saved calls that default to NOPs. The only effects are the
On 06/20/2014 01:21 PM, Alex Williamson wrote:
On Thu, 2014-06-19 at 13:48 +1000, Alexey Kardashevskiy wrote:
On 06/19/2014 11:50 AM, Alexey Kardashevskiy wrote:
On 06/19/2014 10:50 AM, Alexey Kardashevskiy wrote:
On 06/19/2014 04:35 AM, Alex Williamson wrote:
On Wed, 2014-06-18 at 21:36
On Fri, Jun 20, 2014 at 09:53:26AM -0300, Marcelo Tosatti wrote:
On Fri, Jun 20, 2014 at 02:15:10PM +0300, Gleb Natapov wrote:
On Thu, Jun 19, 2014 at 04:00:24PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 12:20:32PM +0300, Gleb Natapov wrote:
CCing Marcelo,
On Wed,
On Jun 16, 2014, at 10:21 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 16/06/2014 18:47, John Nielsen ha scritto:
On Jun 16, 2014, at 10:39 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 16/06/2014 18:09, John Nielsen ha scritto:
The only substantial difference on the hardware side is
The new optional property always-on indicates that the timers
are, well, always on when used with KVM.
This allows for substantial performance improvement in the guest
(it switches to NOHZ instead of using a periodic tick per vcpu)
and removes a lot of burden from the host (no need to inject tons
Hi Andre,
On Thu, Jun 19, 2014 at 01:44:37PM +0100, Andre Przywara wrote:
Extend the vGIC handling code to deal with different IRQ chip devices
instead of hard-coding the GICv2 in.
Minor comment, but there are a few stray pr_infos in here which I don't
think are especially useful.
+
On Fri, Jun 20, 2014 at 05:38:14PM +0100, Marc Zyngier wrote:
The new optional property always-on indicates that the timers
are, well, always on when used with KVM.
This allows for substantial performance improvement in the guest
(it switches to NOHZ instead of using a periodic tick per
Il 20/06/2014 17:41, John Nielsen ha scritto:
So we have a clue. Let me study the code more, I'll try to get back with a
suggestion.
Paolo, have you had an opportunity to look in to this some more?
Not yet, sorry.
One possibility is this though. Can you try migrating (or
On Fri, Jun 20, 2014 at 05:26:22PM +0300, Gleb Natapov wrote:
On Fri, Jun 20, 2014 at 09:53:26AM -0300, Marcelo Tosatti wrote:
On Fri, Jun 20, 2014 at 02:15:10PM +0300, Gleb Natapov wrote:
On Thu, Jun 19, 2014 at 04:00:24PM -0300, Marcelo Tosatti wrote:
On Thu, Jun 19, 2014 at 12:20:32PM
On Fri, Jun 20, 2014 at 05:31:46PM -0300, Marcelo Tosatti wrote:
IIRC your shadow page pinning patch series support flushing of ptes
by mmu notifier by forcing MMU reload and, as a result, faulting in of
pinned pages during next entry. Your patch series does not pin pages
by elevating
On Jun 20, 2014, at 1:53 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 20/06/2014 17:41, John Nielsen ha scritto:
So we have a clue. Let me study the code more, I'll try to get back with
a suggestion.
Paolo, have you had an opportunity to look in to this some more?
Not yet, sorry.
On Thu, 2014-06-19 at 21:21 -0600, Alex Williamson wrote:
Working on big endian being an accident may be a matter of perspective
:-)
The comment remains that this patch doesn't actually fix anything except
the overhead on big endian systems doing redundant byte swapping and
maybe the
On Sat, 2014-06-21 at 00:14 +1000, Alexey Kardashevskiy wrote:
We can still use __raw_writelco, would that be ok?
No unless you understand precisely what kind of memory barriers each
platform require for these.
Cheers,
Ben.
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