On Mon, Jun 23, 2014 at 09:18:33AM +0800, Xuekun Hu wrote:
Thanks, Rik
On Sat, Jun 21, 2014 at 8:58 PM, Rik van Riel r...@redhat.com wrote:
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On 06/21/2014 04:55 AM, Xuekun Hu wrote:
Hi, Rik
I saw your presentation at last year 2013
On Mon, Jun 23, 2014 at 10:08:02AM +0300, Michael S. Tsirkin wrote:
On Mon, Jun 23, 2014 at 09:18:33AM +0800, Xuekun Hu wrote:
Thanks, Rik
On Sat, Jun 21, 2014 at 8:58 PM, Rik van Riel r...@redhat.com wrote:
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On 06/21/2014 04:55
Yes, I would like to test. :-)
On Mon, Jun 23, 2014 at 3:08 PM, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jun 23, 2014 at 10:08:02AM +0300, Michael S. Tsirkin wrote:
On Mon, Jun 23, 2014 at 09:18:33AM +0800, Xuekun Hu wrote:
Thanks, Rik
On Sat, Jun 21, 2014 at 8:58 PM, Rik van
Hello David,
On 20.06.2014 14:15, David Marchand wrote:
Hello,
(as suggested by Paolo, ccing Claudio and kvm mailing list)
Here is a patchset containing an update on ivshmem specs documentation and
importing ivshmem server and client tools.
These tools have been written from scratch and
On Thu, Jun 19, 2014 at 10:52:52AM -0700, Andi Kleen wrote:
Andi Kleen a...@firstfloor.org writes:
Signed-off-by: Kan Liang kan.li...@intel.com
And here I thought that Andi was of the opinion that if you set CPUID to
indicate a particular CPU you had better also handle all its MSRs.
On Wed, Jun 18, 2014 at 03:52:55PM +, Liang, Kan wrote:
diff --git a/arch/x86/kernel/cpu/perf_event.h
b/arch/x86/kernel/cpu/perf_event.h
index 3b2f9bd..f828ddd 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -555,8 +555,9 @@ static inline void
2014-06-23 0:32 GMT-04:00 Venkateswara Rao Nandigam
venkateswararao.nandi...@citrix.com:
It depends on Guest driver. If you look at virtio, the present guest drivers
are implemented this way, I presume there cannot be a better way
functionally. But if someone wants to reduce these
Hi,
we were reading through this quickly today, and these are some of the questions
that
we think can came up when reading this. Answers to some of these questions we
think
we have figured out, but I think it's important to put this information into the
documentation.
I will quote the file in
Sorry, I do not hold rights to share.
-Original Message-
From: David Xu [mailto:davidx...@gmail.com]
Sent: Monday, June 23, 2014 6:25 PM
To: Venkateswara Rao Nandigam
Cc: kvm
Subject: Re: vhost notification model
2014-06-23 0:32 GMT-04:00 Venkateswara Rao Nandigam
On Mon, Jun 16, 2014 at 04:49:18PM -0400, Konrad Rzeszutek Wilk wrote:
Index: linux-2.6/kernel/locking/mcs_spinlock.h
===
--- linux-2.6.orig/kernel/locking/mcs_spinlock.h
+++ linux-2.6/kernel/locking/mcs_spinlock.h
@@ -17,6
Peter Zijlstra pet...@infradead.org writes:
So I really hate this patch, it makes the code hideous. Also, its a
death by a thousand cuts adding endless branches in this code.
FWIW compared to the cost of a RDMSR (which is a very complex operation
for the CPU) the cost of a predicted branch is
On Tue, Jun 17, 2014 at 04:03:29PM -0400, Konrad Rzeszutek Wilk wrote:
+ new = tail | (val _Q_LOCKED_MASK);
+
+ old = atomic_cmpxchg(lock-val, val, new);
+ if (old == val)
+ break;
+
+ val = old;
+ }
+
+ /*
+
On Tue, Jun 17, 2014 at 04:05:31PM -0400, Konrad Rzeszutek Wilk wrote:
+ * The basic principle of a queue-based spinlock can best be understood
+ * by studying a classic queue-based spinlock implementation called the
+ * MCS lock. The paper below provides a good description for this kind
+
On Tue, Jun 17, 2014 at 04:36:15PM -0400, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
On 17.06.14 13:39, Eric Auger wrote:
Hello,
I have a question related to KVM_IRQFD and KVM_SET_GSI_ROUTING ioctl
relationship.
When reading the KVM API documentation I do not understand there is any
dependency between KVM_IRQFD and KVM_SET_GSI_ROUTING. According to the
text it seems only the
2014-06-23 11:38 GMT-04:00 Venkateswara Rao Nandigam
venkateswararao.nandi...@citrix.com:
Sorry, I do not hold rights to share.
That's all right. Based on your evaluation, can your implementation
reduce the VM exit/entry of guest and improve the performance? Thanks.
Regards,
Cong
Hi, All,
I am using a virtual machine in a cloud environment, which means I am
in control of the Guest OS, but have no access to the Host OS. Is
there a simple way to know whether or not the vPMU is enabled or
disabled? Or, is there something I can control so as to turn its state
from enable to
On Mon, Jun 23, 2014 at 1:41 PM, Jidong Xiao jidong.x...@gmail.com wrote:
Hi, All,
I am using a virtual machine in a cloud environment, which means I am
in control of the Guest OS, but have no access to the Host OS. Is
there a simple way to know whether or not the vPMU is enabled or
Hello,
I am planning to study a phd for the next year, and I would like to
spend part on my time studying KVM code in order to suggest new
improvements.
I know that this mail list is used by experts related to KVM, I would
like to ask you, what improvements are needed in KVM in order to
On Mon, 2014-06-23 at 12:14 +1000, Gavin Shan wrote:
The patch synchronizes firmware header file (opal.h) for PCI error
injection
The FW API you expose is not PCI specific. I haven't seen the
corresponding FW patches yet but I'm not fan of that single call
that collates unrelated things.
I
On Tue, Jun 24, 2014 at 07:10:14AM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2014-06-23 at 12:14 +1000, Gavin Shan wrote:
The patch synchronizes firmware header file (opal.h) for PCI error
injection
The FW API you expose is not PCI specific. I haven't seen the
corresponding FW patches yet
On Mon, 2014-06-23 at 12:14 +1000, Gavin Shan wrote:
The patch implements one OPAL firmware sysfs file to support PCI error
injection: /sys/firmware/opal/errinjct, which will be used like the
way described as follows.
According to PAPR spec, there are 3 RTAS calls related to error injection:
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