On Fri, Jan 09, 2015 at 03:28:58PM +, Peter Maydell wrote:
On 9 January 2015 at 14:16, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/01/15 13:03, Peter Maydell wrote:
When we reset a cpu by re-calling KVM_ARM_VCPU_INIT, that doesn't
mean we get a new VMID for it, though, does it? I
Hi Razya,
Thanks for the update.
So that's reasonable I think, and I think it makes sense
to keep working on this in isolation - it's more
manageable at this size.
The big questions in my mind:
- What happens if system is lightly loaded?
E.g. a ping/pong benchmark. How much extra CPU
Hi Paolo,
The following changes since commit b1940cd21c0f4abdce101253e860feff547291b0:
Linux 3.19-rc3 (2015-01-05 17:05:20 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
tags/kvm-arm-fixes-3.19
for you to fetch changes up to
On Fri, Jan 09, 2015 at 08:17:20PM -0800, Mario Smarduch wrote:
This patch adds support for 2nd stage page fault handling while dirty page
logging. On huge page faults, huge pages are dissolved to normal pages, and
rebuilding of 2nd stage huge pages is blocked. In case migration is
canceled
On Thu, Jan 08, 2015 at 05:42:07PM -0800, Mario Smarduch wrote:
This patch enables ARMv8 dirty page logging support. Plugs ARMv8 into generic
layer through Kconfig symbol, and drops earlier ARM64 constraints to enable
logging at architecture layer. I applies cleanly on top patches series
On Fri, Jan 09, 2015 at 02:35:49PM +, Marc Zyngier wrote:
On 09/01/15 12:30, Christoffer Dall wrote:
On Thu, Jan 08, 2015 at 11:59:08AM +, Marc Zyngier wrote:
Let's assume a guest has created an uncached mapping, and written
to that page. Let's also assume that the host uses a
On Mon, Dec 15, 2014 at 06:43:32PM +0100, Eric Auger wrote:
To be more explicit on vgic initialization failure, -ENODEV is
returned by vgic_init when no online vcpus can be found at init.
Signed-off-by: Eric Auger eric.au...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
On Mon, Dec 15, 2014 at 06:43:33PM +0100, Eric Auger wrote:
Since the advent of VGIC dynamic initialization, this latter is
initialized quite late on the first vcpu run or on-demand, when
injecting an IRQ or when the guest sets its registers.
This initialization could be initiated explicitly
From: Marc Zyngier marc.zyng...@arm.com
Commit b856a59141b1 (arm/arm64: KVM: Reset the HCR on each vcpu
when resetting the vcpu) moved the init of the HCR register to
happen later in the init of a vcpu, but left out the fixup
done in kvm_reset_vcpu when preparing for a 32bit guest.
As a result,
From: Marc Zyngier marc.zyng...@arm.com
It took about two years for someone to notice that the IPA passed
to TLBI IPAS2E1IS must be shifted by 12 bits. Clearly our reviewing
is not as good as it should be...
Paper bag time for me.
Reported-by: Mario Smarduch m.smard...@samsung.com
Tested-by:
On Tue, Dec 30, 2014 at 11:19:13AM +0530, Anup Patel wrote:
(dropping previous conversation for easy reading)
Hi Marc/Christoffer,
I tried implementing PMU context-switch via C code
in EL1 mode and in atomic context with irqs disabled.
The context switch itself works perfectly fine but
On 11 January 2015 at 12:33, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Jan 09, 2015 at 03:28:58PM +, Peter Maydell wrote:
But implementations are allowed to hit in the cache even
when the cache is disabled. In particular, setting the guest
But how can it hit anything
On Sun, Jan 11, 2015 at 05:37:52PM +, Peter Maydell wrote:
On 11 January 2015 at 12:33, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Jan 09, 2015 at 03:28:58PM +, Peter Maydell wrote:
But implementations are allowed to hit in the cache even
when the cache is
Removes some functions that are not used anywhere:
cpu_has_vmx_eptp_writeback() cpu_has_vmx_eptp_uncacheable()
This was partially found by using a static code analysis program called
cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
arch/x86/kvm/vmx.c |
On 11 January 2015 at 17:58, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Sun, Jan 11, 2015 at 05:37:52PM +, Peter Maydell wrote:
On 11 January 2015 at 12:33, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Jan 09, 2015 at 03:28:58PM +, Peter Maydell wrote:
But
On Sun, Jan 11, 2015 at 06:27:35PM +, Peter Maydell wrote:
On 11 January 2015 at 17:58, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Sun, Jan 11, 2015 at 05:37:52PM +, Peter Maydell wrote:
On 11 January 2015 at 12:33, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Wed, Dec 03, 2014 at 05:07:09PM +0100, Eric Auger wrote:
Introduce __KVM_HAVE_ARCH_VIRTUAL_INTC_INITIALIZED define and
associated kvm_arch_is_virtual_intc_initialized function. This latter
allows to test whether the virtual interrupt controller is initialized
and ready to accept virtual IRQ
On Wed, Dec 03, 2014 at 05:07:10PM +0100, Eric Auger wrote:
on arm/arm64 the VGIC is dynamically instantiated and it is useful
to expose its state, especially for irqfd setup.
This patch defines __KVM_HAVE_ARCH_VIRTUAL_INTC_INITIALIZED
and implements kvm_arch_is_virtual_intc_initialized
On Wed, Dec 03, 2014 at 05:07:11PM +0100, Eric Auger wrote:
On arm/arm64, the interrupt controller is dynamically instantiated.
There is a risk the user-space assigns an irqfd before this latter
is initialized and ready to accept virtual irq injection. On such
attempt, the IRQFD setup is
On 2014-12-22 09:28:52, Paolo Bonzini wrote:
On 22/12/2014 07:39, Zhang Haoyu wrote:
Hi,
When I perform P2V from native servers with win2008 to kvm vm,
some cases failed due to the physical disk was using GPT for partition,
and QEMU doesn't support GPT by default.
And, I see in below
On Mon, Jan 12, 2015 at 12:41 AM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Tue, Dec 30, 2014 at 11:19:13AM +0530, Anup Patel wrote:
(dropping previous conversation for easy reading)
Hi Marc/Christoffer,
I tried implementing PMU context-switch via C code
in EL1 mode and in
On Wed, Dec 03, 2014 at 05:07:12PM +0100, Eric Auger wrote:
This patch enables irqfd on arm/arm64.
Both irqfd and resamplefd are supported. Injection is implemented
in vgic.c without routing.
This patch enables CONFIG_HAVE_KVM_EVENTFD and CONFIG_HAVE_KVM_IRQFD.
KVM_CAP_IRQFD is now
commit 35d0470668cca234e49ed35342b3f9a0eec8355c upstream
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
Cc: linux-m...@linux-mips.org
Cc: James Hogan james.ho...@imgtec.com
Cc:
commit 18a8cd63c0d800bbc8b91f03054fcb13d308f6ec upstream
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
Cc: linux-m...@linux-mips.org
Cc: James Hogan
commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Some versions of the assembler will not assemble CFC1 for OCTEON, so override
the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to
pick
commit 45b585c8dcdc469bb40b58cc2801acd7a2332525 upstream
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
Cc: linux-m...@linux-mips.org
Cc: James Hogan
commit cd3f5389489146297eb2c11e4f9d1c4e8aaeb59f upstream
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
Cc: linux-m...@linux-mips.org
Cc: David Daney ddaney.c...@gmail.com
Cc: James Hogan james.ho...@imgtec.com
Cc:
Apparently no TLB flush is needed when there's no valid rmap in memory slot.
Signed-off-by: Kai Huang kai.hu...@linux.intel.com
---
arch/x86/kvm/mmu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index f83fc6c..d43bf50 100644
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