On Thu, Mar 12, 2015 at 03:21:29PM +1100, David Gibson wrote:
>On Thu, Mar 12, 2015 at 02:16:42PM +1100, Gavin Shan wrote:
>> On Thu, Mar 12, 2015 at 11:57:21AM +1100, David Gibson wrote:
>> >On Wed, Mar 11, 2015 at 05:34:11PM +1100, Gavin Shan wrote:
>> >> The patch adds one more EEH sub-command (
On Thu, Mar 12, 2015 at 02:16:42PM +1100, Gavin Shan wrote:
> On Thu, Mar 12, 2015 at 11:57:21AM +1100, David Gibson wrote:
> >On Wed, Mar 11, 2015 at 05:34:11PM +1100, Gavin Shan wrote:
> >> The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR)
> >> to inject the specified EEH error, wh
This adds a missing break statement to VFIO_DEVICE_SET_IRQS handler
without which vfio_pci_set_err_trigger() would never be called.
While we are here, add another "break" to VFIO_PCI_REQ_IRQ_INDEX case
so if we add more indexes later, we won't miss it.
Signed-off-by: Alexey Kardashevskiy
---
dr
On Thu, Mar 12, 2015 at 11:57:21AM +1100, David Gibson wrote:
>On Wed, Mar 11, 2015 at 05:34:11PM +1100, Gavin Shan wrote:
>> The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR)
>> to inject the specified EEH error, which is represented by
>> (struct vfio_eeh_pe_err), to the indicated
https://bugzilla.kernel.org/show_bug.cgi?id=94771
Bug ID: 94771
Summary: [Nested kvm on kvm] 32bit win7 guest as L2 guest sho
blue screen
Product: Virtualization
Version: unspecified
Kernel Version: 4.0.0-rc1
Hardware:
On Wed, Mar 11, 2015 at 05:34:11PM +1100, Gavin Shan wrote:
> The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR)
> to inject the specified EEH error, which is represented by
> (struct vfio_eeh_pe_err), to the indicated PE for testing purpose.
>
> Signed-off-by: Gavin Shan
> ---
> D
On Fri, Mar 06, 2015 at 06:51:52AM +, Wu, Feng wrote:
>
>
> > -Original Message-
> > From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
> > Sent: Wednesday, March 04, 2015 8:06 PM
> > To: Wu, Feng
> > Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> > g...@
Ohad Ben-Cohen writes:
> On Mon, Mar 9, 2015 at 10:41 AM, Michael S. Tsirkin wrote:
>> On Sat, Mar 07, 2015 at 08:06:56PM +0100, Michael S. Tsirkin wrote:
>>> virtio spec requires that all drivers set DRIVER_OK
>>> before using devices. While rpmsg isn't yet
>>> included in the virtio 1 spec, pre
On Wed, Mar 11, 2015 at 3:14 PM, Alex Williamson
wrote:
> On Fri, 2015-03-06 at 16:11 -0600, Bjorn Helgaas wrote:
>> On Wed, Mar 04, 2015 at 01:02:43PM -0700, Alex Williamson wrote:
>> > This copies the same support from pci-stub for exactly the same
>> > purpose, enabling a set of PCI IDs to be a
On Fri, 2015-03-06 at 16:11 -0600, Bjorn Helgaas wrote:
> On Wed, Mar 04, 2015 at 01:02:43PM -0700, Alex Williamson wrote:
> > This copies the same support from pci-stub for exactly the same
> > purpose, enabling a set of PCI IDs to be automatically added to the
> > driver's dynamic ID table at mod
* Andrey Korolyov (and...@xdel.ru) wrote:
> On Wed, Mar 11, 2015 at 10:33 PM, Dr. David Alan Gilbert
> wrote:
> > * Kevin O'Connor (ke...@koconnor.net) wrote:
> >> On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote:
> >> > On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
From: Marcel Apfelbaum
Needed to query machine's properties.
Signed-off-by: Marcel Apfelbaum
Acked-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Paolo Bonzini
---
include/sysemu/kvm.h | 2 +-
kvm-all.c| 2 +-
target-arm/kvm.c | 2 +-
target-i386/kvm.c
From: Marcel Apfelbaum
Commit e79d5a6 ("machine: remove qemu_machine_opts global list") removed
the global option descriptions and moved them to MachineState's QOM
properties.
Query kvm-shadow-mem by accessing machine properties through designated
wrappers.
Signed-off-by: Marcel Apfelbaum
Acke
From: Marcel Apfelbaum
Running
x86_64-softmmu/qemu-system-x86_64 -machine pc,kernel_irqchip=on -enable-kvm
leads to crash:
qemu-system-x86_64: qemu/util/qemu-option.c:387: qemu_opt_get_bool_helper:
Assertion `opt->desc && opt->desc->type == QEMU_OPT_BOOL' failed. Aborted
(core du
"Dr. David Alan Gilbert" writes:
> * Kevin O'Connor (ke...@koconnor.net) wrote:
>> On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote:
>> > On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
>> > > For what it's worth, I can't seem to trigger the problem if I move the
>>
On Mon, Mar 9, 2015 at 8:26 AM, Christoffer Dall
wrote:
> On Wed, Mar 04, 2015 at 02:35:52PM +, Alex Bennée wrote:
>> From: Christoffer Dall
>>
>> The current code was negatively indexing the cpu state array and not
>> synchronizing banked spsr register state with the current mode's spsr
>> s
* Kevin O'Connor (ke...@koconnor.net) wrote:
> On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote:
> > On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
> > > For what it's worth, I can't seem to trigger the problem if I move the
> > > cmos read above the SIPI/LAPIC code (
On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote:
> On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
> > For what it's worth, I can't seem to trigger the problem if I move the
> > cmos read above the SIPI/LAPIC code (see patch below).
>
> Ugh!
>
> That's a seabios bug
On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
> For what it's worth, I can't seem to trigger the problem if I move the
> cmos read above the SIPI/LAPIC code (see patch below).
Ugh!
That's a seabios bug. Main processor modifies the rtc index
(rtc_read()) while APs try to clear t
On Wed, Mar 11, 2015 at 05:59:04PM +, Dr. David Alan Gilbert wrote:
> * Kevin O'Connor (ke...@koconnor.net) wrote:
> > On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote:
> > > * Kevin O'Connor (ke...@koconnor.net) wrote:
> > > > So, I couldn't get this to fail on my older A
"Dr. David Alan Gilbert" writes:
> * Kevin O'Connor (ke...@koconnor.net) wrote:
>> On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote:
>> > * Kevin O'Connor (ke...@koconnor.net) wrote:
>> > > So, I couldn't get this to fail on my older AMD machine at all with
>> > > the defaul
"Kevin O'Connor" writes:
> On Wed, Mar 11, 2015 at 01:09:42PM -0400, Bandan Das wrote:
>> "Kevin O'Connor" writes:
>> ...
>> >
>> > Something is very odd here. When I run the above command (on an older
>> > AMD machine) I get:
>> >
>> > Found 128 cpu(s) max supported 128 cpu(s)
>> >
>> > That f
Signed-off-by: Gabriel Somlo
---
hw/i386/smbios.c | 10 --
qemu-options.hx | 4 ++--
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
index f2e9ab6..1341e02 100644
--- a/hw/i386/smbios.c
+++ b/hw/i386/smbios.c
@@ -91,6 +91,7 @@ static s
=
KVM Forum 2015: Call For Participation
August 19-21, 2015 - Sheraton Seattle - Seattle, WA
(All submissions must be received before midnight May 1, 2015)
=
KVM is an i
On 11/03/2015 18:37, Kevin O'Connor wrote:
> > I'm going to check the assembly for a compiler error, but is it
> > possible QEMU is returning incorrect data in cmos index 0x5f?
>
> I checked the SeaBIOS assembler and it looks sane. So, I think the
> question is, why is QEMU sometimes returning
On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote:
> * Kevin O'Connor (ke...@koconnor.net) wrote:
> > So, I couldn't get this to fail on my older AMD machine at all with
> > the default SeaBIOS code. But, when I change the code with the patch
> > below, it failed right away.
[
On Wed, Mar 11, 2015 at 01:09:42PM -0400, Bandan Das wrote:
> "Kevin O'Connor" writes:
> ...
> >
> > Something is very odd here. When I run the above command (on an older
> > AMD machine) I get:
> >
> > Found 128 cpu(s) max supported 128 cpu(s)
> >
> > That first value (1 vs 128) comes from QEMU
"Kevin O'Connor" writes:
...
>
> Something is very odd here. When I run the above command (on an older
> AMD machine) I get:
>
> Found 128 cpu(s) max supported 128 cpu(s)
>
> That first value (1 vs 128) comes from QEMU (via cmos index 0x5f).
> That is, during smp init, SeaBIOS expects QEMU to tel
* Kevin O'Connor (ke...@koconnor.net) wrote:
> On Wed, Mar 11, 2015 at 03:53:07PM +, Dr. David Alan Gilbert wrote:
> > * Kevin O'Connor (ke...@koconnor.net) wrote:
> > > On Wed, Mar 11, 2015 at 01:45:57PM +, Dr. David Alan Gilbert wrote:
> > > > * Bandan Das (b...@redhat.com) wrote:
> > > >
On Wed, Mar 11, 2015 at 03:53:07PM +, Dr. David Alan Gilbert wrote:
> * Kevin O'Connor (ke...@koconnor.net) wrote:
> > On Wed, Mar 11, 2015 at 01:45:57PM +, Dr. David Alan Gilbert wrote:
> > > * Bandan Das (b...@redhat.com) wrote:
> > > > "Dr. David Alan Gilbert" writes:
> > > > > while tr
On Wed, Mar 11, 2015 at 01:45:57PM +, Dr. David Alan Gilbert wrote:
> * Bandan Das (b...@redhat.com) wrote:
> > "Dr. David Alan Gilbert" writes:
> > > while true; do (sleep 5; echo -e
> > > '\001cq\n')|/opt/qemu-try-world3/bin/qemu-system-x86_64 -machine
> > > pc-i440fx-2.0,accel=kvm -m 1024
We're running KVM in with the host passthrough for the cpu. This allows the
guest to have exactly the same definitions for the processor as on the
hypervisor.
We would like to be able to do the same thing for the RAM. From dmidecode, we
do not get the RAM speed.
Would it be possible to have
Implement saving and restoring to KVM state of the Config CP0 registers
(namely Config, Config1, Config2, Config3, Config4, and Config5). These
control the features available to a guest, and a few of the fields will
soon be writeable by a guest so QEMU needs to know about them so as not
to clobber
Support the new KVM_CAP_MIPS_FPU capability, which allows the host's FPU
to be exposed to the KVM guest.
The capability is enabled if the guest core has an FPU according to its
Config1 register. Various config bits are now writeable so that KVM is
aware of the configuration (Config1.FP) and so tha
Add the new floating point and MIPS SIMD Architecture (MSA) KVM register
definitions to kvm.c.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 11 +++
This patchset primarily adds support for FPU and MIPS SIMD Architecture
(MSA) in MIPS KVM guests to QEMU. It depends on the KVM patchset which I
recently submitted to add the corresponding hypervisor support to KVM
("[PATCH 00/20] MIPS: KVM: Guest FPU & SIMD (MSA) support").
All comments welcome.
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée wrote:
> For migration to work we need to sync all of the register state. This is
> especially noticeable when GCC starts using FP registers as spill
> registers even with integer programs.
>
> Signed-off-by: Alex Bennée
>
> diff --git a/target-arm/kvm6
On 11/03/15 14:23, Christoffer Dall wrote:
> We can definitely decide at run-time whether to use the GIC and timers
> or not, and the extra code and data structures that we allocate space
> for is really negligable with this config option, so I don't think it's
> worth the extra complexity of alway
This is a revised patch to the previous submission, adding a check for RH=1/DM=1
in kvm_set_msi_irq.
Currently the DM bit is the only thing used to decide irq->dest_mode
(logical when DM set, physical when unset). Documentation indicates that
the DM bit will be 'ignored' when the RH bit is unset,
Guest user mode can generate a guest MSA Disabled exception on an MSA
capable core by simply trying to execute an MSA instruction. Since this
exception is unknown to KVM it will be passed on to the guest kernel.
However guest Linux kernels prior to v3.15 do not set up an exception
handler for the M
Add base code for supporting FPU in MIPS KVM guests. The FPU cannot yet
be enabled in the guest, we're just laying the groundwork.
Whether the guest's FPU context is loaded is stored in a bit in the
fpu_inuse vcpu member. This allows the FPU to be disabled when the guest
disables it, but keeping t
Various semi-used definitions exist in kvm_host.h for the default guest
config registers. Remove them and use the appropriate values directly
when initialising the Config registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc:
Clean up KVM_GET_ONE_REG / KVM_SET_ONE_REG register definitions for
MIPS, to prepare for adding a new group for FPU & MSA vector registers.
Definitions are added for common bits in each group of registers, e.g.
KVM_REG_MIPS_CP0 = KVM_REG_MIPS | 0x1, for the coprocessor 0
registers.
Signed-off
Add KVM register numbers for the MIPS FPU registers, and implement
access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG ioctls when
the FPU capability is enabled (exposed in a later patch) and present in
the guest according to its Config1.FP bit.
The registers are accessible in the current mo
Sort the registers in the kvm_mips_get_reg() switch by register number,
which puts ERROREPC after the CONFIG registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/mips.c | 6 +++---
1 f
Add base code for supporting the MIPS SIMD Architecture (MSA) in MIPS
KVM guests. MSA cannot yet be enabled in the guest, we're just laying
the groundwork.
As with the FPU, whether the guest's MSA context is loaded is stored in
another bit in the fpu_inuse vcpu member. This allows MSA to be disabl
This patchset primarily adds guest Floating Point Unit (FPU) and MIPS
SIMD Architecture (MSA) support to MIPS KVM, by enabling the host
FPU/MSA while in guest mode.
This patchset depends on Paul Burton's FP/MSA fixes patchset, which will
hopefully make it into 4.0. I'd like to get this into 4.1, s
When handling floating point exceptions (FPEs) and MSA FPEs the Cause
bits of the appropriate control and status register (FCSR for FPEs and
MSACSR for MSA FPEs) are read and cleared before enabling interrupts,
presumably so that it doesn't have to go through the pain of restoring
those bits if the
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée wrote:
> While observing KVM traces I can see additional IRQ calls on pretty much
> every MMIO access which is just plain inefficient. Only update the QEMU
> IRQ level if something has actually changed from last time. Otherwise we
> may be papering over
On 03/11/2015 07:43 AM, Radim Krčmář wrote:
> 2015-03-10 16:39-0600, James Sullivan:
>> On 03/10/2015 08:47 AM, Radim Krčmář wrote:
+ irq->dest_mode = phys ? 0 : (MSI_ADDR_DEST_MODE_LOGICAL);
>>>
>>> (Should be APIC_DEST_LOGICAL. All works because it is a boolean and we
>>> only checked for
On Thu, Mar 05, 2015 at 12:27:42PM +0100, Paolo Bonzini wrote:
>
>
> On 05/03/2015 11:53, Marc Zyngier wrote:
> > > +#ifdef CONFIG_HAVE_KVM_IRQFD
> > > + case KVM_CAP_IRQFD:
> > > + r = vgic_present;
> > > + break;
> > > +#endif
> >
> > Nitpick: we have "select HAVE_KVM_IRQFD", s
On Thu, Mar 05, 2015 at 12:26:06PM +0100, Paolo Bonzini wrote:
> IS_ENABLED gives compile-time checking and keeps the code clearer.
>
> The one exception is inside kvm_vm_ioctl_check_extension, where
> the established idiom is to wrap the case labels with an #ifdef.
>
> Signed-off-by: Paolo Bonzi
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
>
> Signed-off-by: Alex Bennée
> Acked-by: Ch
* Bandan Das (b...@redhat.com) wrote:
> "Dr. David Alan Gilbert" writes:
>
> > * Paolo Bonzini (pbonz...@redhat.com) wrote:
> >>
> >>
> >> On 10/03/2015 19:21, Bandan Das wrote:
> >> > Paolo Bonzini writes:
> >> >
> >> >> On 10/03/2015 17:57, Dr. David Alan Gilbert wrote:
> >> >>> I'm seeing
2015-03-10 16:39-0600, James Sullivan:
> On 03/10/2015 08:47 AM, Radim Krčmář wrote:
> >> + irq->dest_mode = phys ? 0 : (MSI_ADDR_DEST_MODE_LOGICAL);
> >
> > (Should be APIC_DEST_LOGICAL. All works because it is a boolean and we
> > only checked for APIC_DEST_PHYSICAL, which is 0.)
> >
>
> Th
On Thu, Mar 05, 2015 at 02:47:44PM +, Mark Rutland wrote:
> Several dts only list "arm,cortex-a7-gic" or "arm,gic-400" in their GIC
> compatible list, and while this is correct (and supported by the GIC
> driver), KVM will fail to detect that it can support these cases.
>
> This patch adds the
If data is read from PIC with invalid access size, the return data stays
uninitialized even though success is returned.
Fix this by always initializing the data.
Signed-off-by: Petr Matousek
Reported-by: Nadav Amit
---
arch/x86/kvm/i8259.c |1 +
1 files changed, 1 insertions(+), 0 deletio
https://bugzilla.kernel.org/show_bug.cgi?id=86161
--- Comment #4 from Timofey ---
CPU:
Intel(R) Xeon(R) CPU E5-2620 v2 @ 2.10GHz
--
You are receiving this mail because:
You are watching the assignee of the bug.
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a m
https://bugzilla.kernel.org/show_bug.cgi?id=86161
Timofey changed:
What|Removed |Added
CC||timo...@koolin.ru
--- Comment #3 from Timofey
On Wed, 2015-03-11 at 19:54 +1100, Alexey Kardashevskiy wrote:
> > +/* Page size flags for ibm,query-pe-dma-window */
> > +#define DDW_PGSIZE_4K 0x01
> > +#define DDW_PGSIZE_64K 0x02
> > +#define DDW_PGSIZE_16M 0x04
> > +#define DDW_PGSIZE_32M 0x08
> > +#define
On 03/10/2015 01:07 AM, Alexey Kardashevskiy wrote:
This extends iommu_table_group_ops by a set of callbacks to support dynamic
DMA windows management.
query() returns IOMMU capabilities such as default DMA window address and
supported number of DMA windows and TCE table levels.
create_table()
62 matches
Mail list logo