On Mon, Sep 14, 2015 at 11:29:34AM +0200, Eric Auger wrote:
> Christoffer,
> On 09/02/2015 09:58 PM, Christoffer Dall wrote:
> > On Mon, Aug 10, 2015 at 03:21:03PM +0200, Eric Auger wrote:
> >> Implements kvm_vgic_[set|unset]_forward.
> >>
> >> Handle low-level VGIC programming: physical IRQ/guest
On Tue, Sep 08, 2015 at 02:04:15PM +0200, Eric Auger wrote:
> Hi Christoffer,
> On 09/02/2015 09:42 PM, Christoffer Dall wrote:
> > On Mon, Aug 10, 2015 at 03:21:01PM +0200, Eric Auger wrote:
> >> From: Marc Zyngier
> >>
> >> So far, the only use of the HW interrupt facility
Hi Eric,
On Wed, Sep 09, 2015 at 10:41:32AM +0200, Eric Auger wrote:
[...]
> I tried to integrate into the updated state machine for non shared
> mapped IRQ but I fail.
What exactly do you mean when you refer to 'updated state machine' ?
>
> 1) The first problem encountered is how to reset
On Mon, Sep 07, 2015 at 06:45:42PM +0200, Eric Auger wrote:
> Hi Christoffer,
> On 09/04/2015 09:40 PM, Christoffer Dall wrote:
> > Forwarded physical interrupts on arm/arm64 is a tricky concept and the
> > way we deal with them is not apparently easy to understand by reading
> > various specs.
>
On Mon, Sep 14, 2015 at 11:29:53AM +0200, Eric Auger wrote:
> On 09/04/2015 09:40 PM, Christoffer Dall wrote:
> > The arch timer currently uses edge-triggered semantics in the sense that
> > the line is never sampled by the vgic and lowering the line from the
> > timer to the vgic doesn't have any
VPID is used to tag address space and avoid a TLB flush. Currently L0 use
the same VPID to run L1 and all its guests. KVM flushes VPID when switching
between L1 and L2.
This patch advertises VPID to the L1 hypervisor, then address space of L1 and
L2 can be separately treated and avoid TLB
Hi Shannon,
On Fri, Sep 11, 2015 at 04:54:53PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM
> Recent commits to kernel/git/torvalds/linux.git have made the following
> functions able to tolerate NULL arguments:
>
> kmem_cache_destroy (commit 3942d29918522)
> mempool_destroy (commit 4e3ca3e033d1)
> dma_pool_destroy (commit 44d7175da6ea)
How do you think about to extend an other SmPL
On Fri, Aug 28, 2015 at 12:11:17PM +0300, Pavel Fedin wrote:
> Hello!
>
> > It's a bit weird to just sned this as a new patch without replying to my
> > mail from yesterday with feedback
>
> Sorry. But changes are actually minimal, and i remember that i replied to
> you with the promise of
>
Hi Andre,
On Fri, Sep 11, 2015 at 12:21:22PM +0100, Andre Przywara wrote:
> Hi Christoffer,
>
> (actually you are not supposed to reply during your holidays!)
yeah, I know, but I couldn't help myself here.
>
> On 09/09/15 09:49, Christoffer Dall wrote:
> > On Tue, Sep 8, 2015 at 6:57 PM,
On 14/09/15 04:14, Shannon Zhao wrote:
>
>
> On 2015/9/11 18:07, Marc Zyngier wrote:
>> On 11/09/15 09:54, Shannon Zhao wrote:
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN. Add
On Mon, Sep 07, 2015 at 05:32:35PM +0200, Eric Auger wrote:
>
>
> On 09/04/2015 09:40 PM, Christoffer Dall wrote:
> > Currently vgic_process_maintenance() processes dealing with a completed
> > level-triggered interrupt directly, but we are soon going to reuse this
> > logic for level-triggered
On 2015/9/14 19:53, Christoffer Dall wrote:
Hi Shannon,
On Fri, Sep 11, 2015 at 04:54:53PM +0800, Shannon Zhao wrote:
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one
On 09/10/2015 02:01 AM, Scott Wood wrote:
> On Fri, 2015-09-04 at 15:46 +0300, Laurentiu Tudor wrote:
>> This way we get rid of an entire file with mostly
>> duplicated code plus a Kconfig option that you always
>> had to take care to check it in order for kvm to work.
>>
>> Signed-off-by:
On 2015-09-14 14:52, Wanpeng Li wrote:
> VPID is used to tag address space and avoid a TLB flush. Currently L0 use
> the same VPID to run L1 and all its guests. KVM flushes VPID when switching
> between L1 and L2.
>
> This patch advertises VPID to the L1 hypervisor, then address space of L1
Sorry, I forgot the changlog. Below are the main changes of this v2
patchset.
Changes since v1->v2:
* Use switch...case for registers access handler instead of adding
alone handler for each register
* Try to use the sys_regs to store the register value instead of adding
new variables in
> Am 14.09.2015 um 15:17 schrieb Laurentiu Tudor :
>
>> On 09/10/2015 02:01 AM, Scott Wood wrote:
>>> On Fri, 2015-09-04 at 15:46 +0300, Laurentiu Tudor wrote:
>>> This way we get rid of an entire file with mostly
>>> duplicated code plus a Kconfig option that you always
On Mon, 2015-09-14 at 16:17 +0300, Laurentiu Tudor wrote:
> On 09/10/2015 02:01 AM, Scott Wood wrote:
> > On Fri, 2015-09-04 at 15:46 +0300, Laurentiu Tudor wrote:
> > > This way we get rid of an entire file with mostly
> > > duplicated code plus a Kconfig option that you always
> > > had to take
On Mon, 2015-09-14 at 16:14 +0200, Alexander Graf wrote:
> > Am 14.09.2015 um 15:17 schrieb Laurentiu Tudor :
> >
> > > On 09/10/2015 02:01 AM, Scott Wood wrote:
> > > > On Fri, 2015-09-04 at 15:46 +0300, Laurentiu Tudor wrote:
> > > > This way we get rid of an entire file
On 14/09/15 16:06, Will Deacon wrote:
> When restoring the system register state for an AArch32 guest at EL2,
> writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
> which can lead to the guest effectively running with junk in the DACR
> and running into unexpected domain faults.
Wanpeng Li writes:
> VPID is used to tag address space and avoid a TLB flush. Currently L0 use
> the same VPID to run L1 and all its guests. KVM flushes VPID when switching
> between L1 and L2.
>
> This patch advertises VPID to the L1 hypervisor, then address space of
Hi Christoffer,
just one small nit I stumbled upon:
On 04/09/15 20:40, Christoffer Dall wrote:
> diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
> index 9ed8d53..f4ea950 100644
> --- a/virt/kvm/arm/vgic.c
> +++ b/virt/kvm/arm/vgic.c
> @@ -1422,34 +1422,43 @@ static bool
When restoring the system register state for an AArch32 guest at EL2,
writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
which can lead to the guest effectively running with junk in the DACR
and running into unexpected domain faults.
This patch works around the issue by
On 14/09/2015 10:58, Stefan Geißler wrote:
>
> I am currently analyzing the delay between vulnerability disclosure (CVE
> release) and the release of a corresponding patch.
>
> Firstly, i noticed that some vulnerabilities are patched before the CVE
> was assigned. How is that possible? Was the
On 11/09/2015 08:12, Wei Yang wrote:
> After 'commit 0b8ba4a2b658 ("KVM: fix checkpatch.pl errors in
> kvm/coalesced_mmio.h")', the declaration of the two function will exceed 80
> characters.
>
> This patch reduces the TAPs to make each line in 80 characters.
>
> Signed-off-by: Wei Yang
On Mon, Sep 14, 2015 at 04:46:28PM +0100, Marc Zyngier wrote:
> On 14/09/15 16:06, Will Deacon wrote:
> > When restoring the system register state for an AArch32 guest at EL2,
> > writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
> > which can lead to the guest effectively
On Sat, 2015-09-12 at 01:11 +, Rustad, Mark D wrote:
> Alex,
>
> > On Sep 11, 2015, at 11:16 AM, Alex Williamson
> > wrote:
> >
> > RFC - Is this something we should do?
>
> Superficially this looks pretty good. I need to think harder to be sure of
> the
On 14/09/2015 20:59, Stefan Geißler wrote:
>>
>> There could be many reasons. For example the problem could be very
>> minor, the patches could have problems, or a second patch was needed
>> because the first fix was insufficient so. It's difficult to say
>> without seeing the CVE and patch
> On Sep 11, 2015, at 6:11 PM, Rustad, Mark D wrote:
>
> Superficially this looks pretty good. I need to think harder to be sure of
> the details.
This is the first time I've looked at all at any of the vfio code, but this is
still looking good to me. Thanks for
From: Houcheng
This patch is to build qemu in android ndk tool-chain, and has been tested in
both
x86_64 and x86 android platform with hardware virtualization enabled. This
patch is
composed of three part:
- configure scripts for android
- OS dependent code
From: Houcheng
This patch is to build qemu in android ndk tool-chain, and has been tested in
both
x86_64 and x86 android platform with hardware virtualization enabled. This
patch is
composed of three part:
- configure scripts for android
- OS dependent code
On Mon, Sep 14, 2015 at 08:32:36AM +0200, Thomas Huth wrote:
> On 14/09/15 04:15, David Gibson wrote:
> > On Fri, Sep 11, 2015 at 11:17:01AM +0200, Thomas Huth wrote:
> >> The PAPR interface defines a hypercall to pass high-quality
> >> hardware generated random numbers to guests. Recent kernels
First of all, Paolo, thanks a lot for your review on this series, it really
means a lot!:)
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org
> [mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Paolo Bonzini
> Sent: Friday, September 11, 2015 7:21 PM
> To: Wu, Feng;
I am currently analyzing the delay between vulnerability disclosure (CVE
release) and the release of a corresponding patch.
Firstly, i noticed that some vulnerabilities are patched before the CVE
was assigned. How is that possible? Was the vulnerability "accitendally"
fixed? (Example: According
On 14/09/15 04:15, David Gibson wrote:
> On Fri, Sep 11, 2015 at 11:17:01AM +0200, Thomas Huth wrote:
>> The PAPR interface defines a hypercall to pass high-quality
>> hardware generated random numbers to guests. Recent kernels can
>> already provide this hypercall to the guest if the right
Hello all,
I am currently analyzing the delay between vulnerability disclosure (CVE
release) and the release of a corresponding patch.
Firstly, i noticed that some vulnerabilities are patched before the CVE
was assigned. How is that possible? Was the vulnerability "accitendally"
fixed?
Christoffer,
On 09/02/2015 09:58 PM, Christoffer Dall wrote:
> On Mon, Aug 10, 2015 at 03:21:03PM +0200, Eric Auger wrote:
>> Implements kvm_vgic_[set|unset]_forward.
>>
>> Handle low-level VGIC programming: physical IRQ/guest IRQ mapping,
>> list register cleanup, VGIC state machine. Also
On 09/04/2015 09:40 PM, Christoffer Dall wrote:
> The arch timer currently uses edge-triggered semantics in the sense that
> the line is never sampled by the vgic and lowering the line from the
> timer to the vgic doesn't have any affect on the pending state of
s/affect/effect
> virtual interrupts
If there is already some polling ongoing, it's impossible to disable the
polling, since as soon as somebody sets halt_poll_ns to 0, polling will
never stop, as grow and shrink are only handled if halt_poll_ns is != 0.
This patch fix it by reset vcpu->halt_poll_ns in order to stop polling
when
On 13/09/2015 14:15, Julia Lawall wrote:
> Remove unneeded NULL test.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> //
> @@ expression x; @@
> -if (x != NULL)
> \(kmem_cache_destroy\|mempool_destroy\|dma_pool_destroy\)(x);
> //
>
>
On 9/10/15 3:13 PM, Christian Borntraeger wrote:
Am 10.09.2015 um 03:55 schrieb Wanpeng Li:
On 9/9/15 9:39 PM, Christian Borntraeger wrote:
Am 03.09.2015 um 16:07 schrieb Wanpeng Li:
v6 -> v7:
* explicit signal (set a bool)
* fix the tracepoint
v5 -> v6:
* fix wait_ns and poll_ns
41 matches
Mail list logo