Hi,
On 11/12/14 17:15, Will Deacon wrote:
On Thu, Dec 11, 2014 at 04:30:33PM +, Andre Przywara wrote:
Currently we describe every interrupt for each device in the FDT
as being edge triggered.
Add a parameter to the irq property generation to allow devices to
specify their interrupts
Among the architectures supported by kvmtool, only x86 defines a
bzImage format. So we shouldn't bother users of other architectures
with a message about something that cannot work.
Make the bzImage check dependent on compiling for x86.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Currently we describe every interrupt for each device in the FDT
as being edge triggered.
Add a parameter to the irq property generation to allow devices to
specify their interrupts as level triggered if needed.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
tools/kvm/arm/fdt.c
the interrupts.
This goes along the lines of a similar QEMU patch:
http://git.qemu.org/?p=qemu.git;a=commitdiff;h=0be969a2d974971628fc4ed95834d22ecf0fd497
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
tools/kvm/hw/serial.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
node (and also match the address size we formely posted)
and let Linux thus read the right values.
This fixes initrd functionality for ARM and ARM64 guests.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/arm/fdt.c |4 ++--
1 file
every time ;-)
Cheers,
Andre.
Andre Przywara (4):
kvmtool: ARM: fix initrd functionality
kvmtool: ARM: allow level interrupts in device tree
kvmtool: ARM: advertise 8250 IRQs as level-triggered
kvmtool: remove warning about bzImage on non-x86 architectures
tools/kvm/arm/fdt.c
of code.
Remove the unreachable snippet.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Andre Przywara andre.przyw...@arm.com
I agree on this. Would it make sense to rewrite this function a bit to
make it more clearer what happens? I find the nesting
Hi,
On 24/11/14 10:10, Eric Auger wrote:
On 11/24/2014 10:47 AM, Christoffer Dall wrote:
On Sun, Nov 23, 2014 at 06:56:57PM +0100, Eric Auger wrote:
This patch series enables irqfd on arm and arm64.
Irqfd framework enables to inject a virtual IRQ into a guest upon an
eventfd trigger.
Hi Nikolay,
On 13/11/14 11:37, Marc Zyngier wrote:
[fixing Andre's email address]
On 13/11/14 11:20, Christoffer Dall wrote:
On Thu, Nov 13, 2014 at 12:45:42PM +0200, Nikolay Nikolaev wrote:
[...]
Going through the vgic_handle_mmio we see that it will require large
refactoring:
-
Hi Nikolay,
On 13/11/14 12:29, Nikolay Nikolaev wrote:
On Thu, Nov 13, 2014 at 1:52 PM, Andre Przywara andre.przyw...@arm.com
wrote:
Hi Nikolay,
On 13/11/14 11:37, Marc Zyngier wrote:
[fixing Andre's email address]
On 13/11/14 11:20, Christoffer Dall wrote:
On Thu, Nov 13, 2014 at 12:45
On 13/11/14 15:02, Nikolay Nikolaev wrote:
On Thu, Nov 13, 2014 at 4:23 PM, Eric Auger eric.au...@linaro.org wrote:
On 11/13/2014 03:16 PM, Eric Auger wrote:
On 11/13/2014 11:45 AM, Nikolay Nikolaev wrote:
On Mon, Nov 10, 2014 at 6:27 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
Hi Christoffer,
On 15/10/14 17:25, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:44PM +0100, Andre Przywara wrote:
Currently we only need to deal with one MMIO region for the GIC
emulation, but we soon need to extend this. Refactor the existing
code to allow easier addition
Hi Christoffer,
On 15/10/14 17:26, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:45PM +0100, Andre Przywara wrote:
Some GICv3 registers can and will be accessed as 64 bit registers.
Currently the register handling code can only deal with 32 bit
accesses, so we do two consecutive calls
Hi Christoffer,
On 15/10/14 17:27, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:46PM +0100, Andre Przywara wrote:
Currently we only have one virtual GIC model supported, so all guests
use the same emulation code. With the addition of another model we
end up with different guests
Hi Christoffer,
On 15/10/14 17:25, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:42PM +0100, Andre Przywara wrote:
The virtual MPIDR registers (containing topology information) for the
guest are currently mapped linearily to the vcpu_id. Improve this
mapping for arm64 by using three
On 15/10/14 17:27, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:47PM +0100, Andre Przywara wrote:
Currently the maximum number of vCPUs supported is a global value
limited by the used GIC model. GICv3 will lift this limit, but we
still need to observe it for guests using GICv2.
So
On 08/10/14 05:08, wanghaibin wrote:
On 2014/8/21 21:06, Andre Przywara wrote:
GICv3 is the ARM generic interrupt controller designed to overcome
some limits of the prevalent GICv2. Most notably it lifts the 8-CPU
limit. Though with recent patches from Marc there is support for
hosts
for Aarch32 and Aarch64 guest
4. System event exit reason
Thanks for the quick respin. Looks fine now for me.
For the whole v5 series:
Reviewed-by: Andre Przywara andre.przyw...@arm.com
Cheers,
Andre.
Changes since v4:
- Avoid using magic '0' target for kvm arm generic target
- Added
Hi Christoffer,
On 28/09/14 15:04, Christoffer Dall wrote:
The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
store these as an array of two such registers on the vgic vcpu struct.
However, we access them as a single 64-bit value or as a bitmap pointer
in the generic vgic
Hi Anup,
thanks for the re-spin and sorry for the delay.
Looks better now, some minor comments below.
On 19/09/14 00:57, Anup Patel wrote:
Instead, of trying out each and every target type we should
use KVM_ARM_PREFERRED_TARGET vm ioctl to determine target type
for KVM ARM/ARM64.
If
remove the braces here.
Given that you fix that:
Reviewed-by: Andre Przywara andre.przyw...@arm.com
Thanks!
Andre
+ } else {
+ _FDT(fdt_property_string(fdt, compatible, arm,psci));
+ fns = psci_0_1_fns;
+ }
_FDT(fdt_property_string(fdt, method, hvc
;
default: {
bool ret;
Looks good to me.
Reviewed-by: Andre Przywara andre.przyw...@arm.com
Cheers,
Andre.
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To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http
On 19/09/14 00:57, Anup Patel wrote:
The VCPU target type KVM_ARM_TARGET_XGENE_POTENZA is available
in latest Linux-3.16-rcX or higher hence register aarch64 target
type for it.
This patch enables us to run KVMTOOL on X-Gene Potenza host.
I still don't like the addition of another CPU, but
node (and also match the address size we formely posted)
and let Linux thus read the right values.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
tools/kvm/arm/fdt.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/kvm/arm/fdt.c b/tools/kvm/arm/fdt.c
index
Hi Anup,
On 08/09/14 09:17, Anup Patel wrote:
Instead, of trying out each and every target type we should
use KVM_ARM_PREFERRED_TARGET vm ioctl to determine target type
for KVM ARM/ARM64.
If KVM_ARM_PREFERRED_TARGET vm ioctl fails then we fallback to
old method of trying all known target
Anup,
On 08/09/14 09:17, Anup Patel wrote:
The VCPU target type KVM_ARM_TARGET_XGENE_POTENZA is available
in latest Linux-3.16-rcX or higher hence register aarch64 target
type for it.
This patch enables us to run KVMTOOL on X-Gene Potenza host.
Why do you need this still if the previous
On 08/09/14 09:17, Anup Patel wrote:
The KVM_EXIT_SYSTEM_EVENT exit reason was added to define
architecture independent system-wide events for a Guest.
Currently, it is used by in-kernel PSCI-0.2 emulation of
KVM ARM/ARM64 to inform user space about PSCI SYSTEM_OFF
or PSCI SYSTEM_RESET
Hi wanghaibin,
On 05/09/14 04:28, wanghaibin wrote:
On 2014/8/21 21:06, Andre Przywara wrote:
+void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
+{
+struct kvm *kvm = vcpu-kvm;
+struct kvm_vcpu *c_vcpu;
+struct vgic_dist *dist = kvm-arch.vgic;
+u16 target_cpus
(resent, that was the wrong account before ...)
Hi Anup,
On 26/08/14 10:22, Anup Patel wrote:
Instead, of trying out each and every target type we should
use KVM_ARM_PREFERRED_TARGET vm ioctl to determine target type
for KVM ARM/ARM64.
If KVM_ARM_PREFERRED_TARGET vm ioctl fails then we
Hi Anup,
On 26/08/14 10:22, Anup Patel wrote:
If in-kernel KVM support PSCI-0.2 emulation then we should set
KVM_ARM_VCPU_PSCI_0_2 feature for each guest VCPU and also
provide arm,psci-0.2,arm,psci as PSCI compatible string.
This patch updates kvm_cpu__arch_init() and setup_fdt() as
per
On 29/08/14 17:17, Will Deacon wrote:
On Fri, Aug 29, 2014 at 10:10:52AM +0100, Andre Przywara wrote:
(resent, that was the wrong account before ...)
Aha, and now your true identity has been revealed to all! Nice try Andre...
or should I say, Rienhard?
Psst, don't give Google funny ideas
in struct kvm_arch, but keep it down to
8 for now.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/include/asm/kvm_host.h |1 +
arch/arm/kvm/arm.c|6 ++
arch/arm64/include/asm/kvm_host.h |3 +++
virt/kvm/arm/vgic-v2.c|5
into a new file (vgic-v3-emul.c).
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/kvm/Makefile|1 +
include/kvm/arm_vgic.h | 11 +-
include/linux/irqchip/arm-gic-v3.h | 26 ++
include/linux/kvm_host.h |1 +
include/uapi/linux/kvm.h
don't
provide MMIO regions for the virtual CPU interface in the DT), but
restrict those hosts to use GICv3 guests only.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic-v3.c | 168 +++-
virt/kvm/arm/vgic.c|2 +
2 files
.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 93 ---
1 file changed, 52 insertions(+), 41 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 5e0bc24..e8f92b2 100644
--- a/virt/kvm/arm/vgic.c
userland code to make use of that feature and
explicitly ask for a virtual GICv3.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/include/uapi/asm/kvm.h |7 ++
include/kvm/arm_vgic.h|4 ++--
virt/kvm/arm/vgic-v3-emul.c |3 +++
virt/kvm/arm/vgic.c
Some GICv3 registers can and will be accessed as 64 bit registers.
Currently the register handling code can only deal with 32 bit
accesses, so we do two consecutive calls to cover this.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 48
.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
As the diff isn't always obvious here (and to aid eventual rebases),
here is a list of high-level changes done to the code:
* added new file to respective arm/arm64 Makefiles
* moved definitions and prototypes from vgic.c to vgic.h
MPIDR.
Use this new accessor in the PSCI emulation.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/include/asm/kvm_emulate.h |2 +-
arch/arm/include/asm/kvm_host.h |2 ++
arch/arm/kvm/arm.c | 15 +++
arch/arm/kvm/psci.c
registers on a
world switch, but actually disallow a guest to change it by only
restoring a fixed, once-initialized value.
This value depends on the GIC model userland has chosen for a guest.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/kernel/asm-offsets.c |1 +
arch/arm64/kvm
function pointers for those
functions that are different and provide the necessary code to
initialize them.
This includes functions that depend on the emulated GIC model only
and functions that depend on the combination of host and guest GIC.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/kvm/coproc.c | 19 +++
arch/arm64/kvm/sys_regs.c | 26 ++
virt/kvm/arm/vgic-v3-emul.c |2 +-
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm
into the accessors, extend them to
take an opaque private pointer parameter.
For the current GICv2 emulation we ignore it and simply pass NULL
on the call.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic-v2-emul.c | 41 -
virt/kvm/arm
With the introduction of a second emulated GIC model we need to let
userspace specify the GIC model to use for each VM. Pass the
userspace provided value down into the vGIC code to differentiate
later.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/kvm/arm.c |2
* remove double definition of VCPU_NOT_ALLOCATED
* some code move-around
* whitespace fixes
Andre Przywara (15):
arm/arm64: KVM: rework MPIDR assignment and add accessors
arm/arm64: KVM: pass down user space provided GIC type into vGIC code
arm/arm64: KVM: refactor vgic_handle_mmio() function
Currently we only need to deal with one MMIO region for the GIC
emulation, but we soon need to extend this. Refactor the existing
code to allow easier addition of different ranges without code
duplication.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 72
vgic_set_attr() and vgic_get_attr() contain both code specific for
the emulated GIC as well as code for the userland facing, generic
part of the GIC.
Split the guest GIC facing code of from the generic part to allow
easier splitting later.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
/kernel/git/maz/arm-platforms.git
to get all of GICv3 host, vgic-dyn and the GICv3 guest emualation stuff
at once.
Regards,
Andre.
From: kvmarm-boun...@lists.cs.columbia.edu
kvmarm-boun...@lists.cs.columbia.edu on behalf of Andre Przywara
andre.przyw
On 19/06/14 22:15, Chalamarla, Tirumalesh wrote:
-Original Message-
From: kvmarm-boun...@lists.cs.columbia.edu
[mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Andre Przywara
Sent: Thursday, June 19, 2014 2:46 AM
To: linux-arm-ker...@lists.infradead.org; kvm
On 19/06/14 22:43, Chalamarla, Tirumalesh wrote:
-Original Message-
From: kvmarm-boun...@lists.cs.columbia.edu
[mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Andre Przywara
Sent: Thursday, June 19, 2014 2:46 AM
To: linux-arm-ker...@lists.infradead.org; kvm
registers on a
world switch, but actually disallow a guest to change it by only
restoring a fixed, once-initialized value.
This value depends on the GIC model userland has chosen for a guest.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/kernel/asm-offsets.c |1 +
arch/arm64/kvm
-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/kvm/coproc.c | 19 +++
arch/arm64/kvm/sys_regs.c | 26 ++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index c58a351..4adadb7 100644
--- a/arch/arm
into a new file (vgic-v3-emul.c).
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/kvm/Makefile|1 +
include/kvm/arm_vgic.h | 11 +-
include/linux/irqchip/arm-gic-v3.h | 26 ++
include/linux/kvm_host.h |1 +
include/uapi/linux/kvm.h
function pointers for those
functions that are different and provide the necessary code to
initialize them.
This includes functions that depend on the emulated GIC model only
and functions that depend on the combination of host and guest GIC.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/kvm/Makefile |1 +
arch/arm64/kvm/Makefile |1 +
virt/kvm/arm/vgic-v2-emul.c | 795
virt/kvm/arm/vgic.c | 856 +++
virt/kvm
Currently we only need to deal with one MMIO region for the GIC
emulation, but we soon need to extend this. Refactor the existing
code to allow easier addition of different ranges without code
duplication.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 72
With the introduction of a second emulated GIC model we need to let
userspace specify the GIC model to use for each VM. Pass the
userspace provided value down into the vGIC code to differentiate
later.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/kvm/arm.c |2
in struct kvm_arch, but keep it down to
8 for now.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/include/asm/kvm_host.h |1 +
arch/arm/kvm/arm.c|6 ++
arch/arm64/include/asm/kvm_host.h |3 +++
virt/kvm/arm/vgic-v2.c|5
.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 93 ---
1 file changed, 52 insertions(+), 41 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 2de58b3..2a59dff 100644
--- a/virt/kvm/arm/vgic.c
userland code to make use of that feature and
explicitly ask for a virtual GICv3.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/include/uapi/asm/kvm.h |7 ++
include/kvm/arm_vgic.h|4 ++--
virt/kvm/arm/vgic-v3-emul.c |3 +++
virt/kvm/arm/vgic.c
be grateful for people to test for GICv2 regressions also
(so on a GICv2 host with current kvmtool/qemu), as there is quite
some refactoring on that front.
Much of the code was inspired by Marc, so send all praises to him
(while I take the blame).
Cheers,
Andre.
Andre Przywara (14):
arm/arm64: KVM
into the accessors, extend them to
take an opaque private pointer parameter.
For the current GICv2 emulation we ignore it and simply pass NULL
on the call.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic-v2-emul.c | 41 -
virt/kvm/arm
don't
provide MMIO regions for the virtual CPU interface in the DT), but
restrict those hosts to use GICv3 guests only.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic-v3.c | 138 ++--
virt/kvm/arm/vgic.c|2 +
2 files
Some GICv3 registers can and will be accessed as 64 bit registers.
Currently the register handling code can only deal with 32 bit
accesses, so we do two consecutive calls to cover this.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
virt/kvm/arm/vgic.c | 48
MPIDR.
Use this new accessor in the PSCI emulation.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm/include/asm/kvm_emulate.h |2 +-
arch/arm/include/asm/kvm_host.h |2 ++
arch/arm/kvm/arm.c | 15 +++
arch/arm/kvm/psci.c
The code currently is assuming fixed sized memory regions for the
distributor and CPU interface. GICv3 needs a dynamic allocation of
it's redistributor region, since it's size depends on the number of
vCPUs.
Also add the necessary code to create a GICv3 IRQ chip instance.
Signed-off-by: Andre
Extend the vGIC handling code to deal with different IRQ chip devices
instead of hard-coding the GICv2 in.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
tools/kvm/arm/aarch64/arm-cpu.c|2 +-
tools/kvm/arm/gic.c| 59
Add the command line parameter --gicv3 to request GICv3 emulation
in the kernel. Connect that to the already existing GICv3 code.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
tools/kvm/arm/aarch64/arm-cpu.c|5 -
.../kvm/arm/aarch64/include/kvm/kvm-config
kvmtool version first.
Cheers,
Andre
Andre Przywara (4):
kvmtool: public header definitions from GICv3 emulation patch series
kvmtool: prepare for instantiating different IRQ chip devices
kvmtool: add support for supplying GICv3 redistributor addresses
kvmtool: add command line parameter
This pulls the necessary defines for the GICv3 constants from the
Linux tree into kvmtool for now. Should be obsolete as soon as
the vGICv3 patches are upstream and kvmtool is rebased on top of
it.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
arch/arm64/include/uapi/asm/kvm.h |6
list, since
they need special accessor functions and the arch timer is optional.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
Changes from v1:
- move code out of coproc.c and into guest.c and arch_timer.c
- present
On 12/13/2013 09:10 PM, Christoffer Dall wrote:
On Fri, Dec 13, 2013 at 02:23:26PM +0100, Andre Przywara wrote:
For migration to work we need to save (and later restore) the state of
each core's virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
On 12/12/2013 10:23 AM, Peter Maydell wrote:
On 12 December 2013 02:28, Christoffer Dall christoffer.d...@linaro.org wrote:
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index a30035d..9565e6a 100644
--- a/Documentation/virtual/kvm/api.txt
+++
From: Andre Przywara andre.przyw...@calxeda.com
For migration to work we need to save (and later restore) the state of
each cores virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
the three needed registers (control, counter, compare value).
Though
On 12/10/2013 11:50 AM, Andre Przywara wrote:
From: Andre Przywara andre.przyw...@calxeda.com
Ooops, I managed to screw up the authorship :-( Can the committer please
change this to: Andre Przywara andre.przyw...@linaro.org (as in the
signed-off-by?)
Thanks,
Andre.
For migration to work
On Wed, 10 Apr 2013 01:46:02 +0200
Borislav Petkov b...@alien8.de wrote:
Hi guys,
so I was trying to repro tglx's bug in smpboot.c and for some reason,
the most reliable way to trigger it was to boot an 32-bit atom smp
guest in kvm (don't ask :)).
The problem, however, was that atom
On Wed, 10 Apr 2013 13:08:46 +0300
Gleb Natapov g...@redhat.com wrote:
On Wed, Apr 10, 2013 at 11:29:42AM +0200, Andre Przywara wrote:
In a real world VendorSpecific should be replaced with something
more meaningful. Depends on KVMs intention to emulate instructions,
actually out of scope
to figure out what are the
expectations/requirements, to know _which_ changes will be needed.
On Tue, Apr 24, 2012 at 02:19:25PM -0300, Eduardo Habkost wrote:
(CCing Andre Przywara, in case he can help to clarify what's the
expected meaning of -cpu host)
[...]
I am not sure I understand what
/lkml/2011/6/22/20]
Any help will be appreciated.
Prateek
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Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
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there is a real framework for dealing with
P-state hints from the guest OS, I'd be reluctant with quick and dirty
emulations.
Thanks,
Andre.
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Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
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this.
Regards,
Andre.
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Andre Przywara
AMD-OSRC (Dresden)
Tel: x29712
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array indicies
and fills the entry before querying it's value.
This fixes AVX support in KVM guests.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/x86.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
When iterating through the XSAVE feature enumeration CPUID leaf (0xD)
we should not stop at the first zero EAX, but instead keep scanning
since there are gaps in the enumeration (ECX=1 for instance).
This fixes the proper usage of AVX in KVM guests.
Signed-off-by: Andre Przywara andre.przyw
When iterating through the XSAVE feature enumeration CPUID leaf (0xD)
we should not stop at the first zero EAX, but instead keep scanning
since there are gaps in the enumeration (ECX=1 for instance).
This fixes the proper usage of AVX in KVM guests.
Signed-off-by: Andre Przywara andre.przyw
Avi Kivity wrote:
On 03/30/2011 03:01 PM, Andre Przywara wrote:
If KVM cannot find an exact match for a requested CPUID leaf, the
code will try to find the closest match instead of simply confessing
it's failure. The heuristic is on one hand wrong nowadays,
since it does not take the KVM CPUID
values were returned in response to
a CPUID intercept.
CC: sta...@kernel.org [2.6.38]
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/x86.c | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index
Avi Kivity wrote:
On 03/31/2011 03:13 PM, Andre Przywara wrote:
If KVM cannot find an exact match for a requested CPUID leaf, the
code will try to find the closest match instead of simply confessing
it's failure.
The implementation was meant to satisfy the CPUID specification, but
did
values were returned in response to
a CPUID intercept.
CC: sta...@kernel.org [2.6.38]
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/x86.c | 31 +--
1 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm
and simply skip zero
ones to also cover later features.
CC: sta...@kernel.org [2.6.38]
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/x86.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index bfd7763
-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/x86.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 6e86cec..625143f 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -4959,12 +4959,6 @@ struct
Roedel, Joerg wrote:
On Tue, Feb 08, 2011 at 07:22:29PM -0500, Andre Przywara wrote:
Somehow the code line advancing the RIP and checking for exceptions
got dropped between the post on the ML and the commit.
Add it again to let guests boot on upcoming AMD CPUs again.
Reported-by: Joerg Roedel
Somehow the code line advancing the RIP and checking for exceptions
got dropped between the post on the ML and the commit.
Add it again to let guests boot on upcoming AMD CPUs again.
Reported-by: Joerg Roedel joerg.roe...@amd.com
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86
Hi,
this is version 3 of the DecodeAssist patches.
I added 3 clean up patches which are not SVM specific.
Changes between v2 and v3:
- now includes the (unchanged) CR8 handling fix
- move complete_insn_gp() helper function into x86.c
- remove unnecessary comment
- fix handling of illegal CR
Newer SVM implementations provide the GPR number in the VMCB, so
that the emulation path is no longer necesarry to handle debug
register access intercepts. Implement the handling in svm.c and
use it when the info is provided.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm
the recent APM Vol.2 and the recent AMD CPUID specification describe
new CPUID features bits for SVM. Name them here for later usage.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/svm.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/x86
In case of a nested page fault or an intercepted #PF newer SVM
implementations provide a copy of the faulting instruction bytes
in the VMCB.
Use these bytes to feed the instruction emulator and avoid the costly
guest instruction fetch in this case.
Signed-off-by: Andre Przywara andre.przyw
move the complete_insn_gp() helper function out of the VMX part
into the generic x86 part to make it usable by SVM.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/include/asm/kvm_host.h |2 ++
arch/x86/kvm/vmx.c | 16
arch/x86/kvm/x86.c
emulate_instruction had many callers, but only one used all
parameters. One parameter was unused, another one is now
hidden by a wrapper function (required for a future addition
anyway), so most callers use now a shorter parameter list.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
The handling of CR8 writes in KVM is currently somewhat cumbersome.
This patch makes it look like the other CR register handlers
and fixes a possible issue in VMX, where the RIP would be incremented
despite an injected #GP.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86
When the DecodeAssist feature is available, the linear address
is provided in the VMCB on INVLPG intercepts. Use it directly to
avoid any decoding and emulation.
This is only useful for shadow paging, though.
Signed-off-by: Andre Przywara andre.przyw...@amd.com
---
arch/x86/kvm/svm.c |7
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