[PATCH] introduce module parameter for ignoring unknown MSRs accesses

reads will return 0, while MSR writes are simply dropped. In both cases we print a message to dmesg to inform the user about that. You can change the behaviour at any time by saying: # echo 1 > /sys/modules/kvm/parameters/ignore_msrs Signed-off-by: Andre Przywara --- arch/x86/kvm

[Qemu-devel] KVMs default CPU type (was: allow sysenter on 32bit guests running on vmx host)

tored when saving/migrating and loaded exactly the same on other hosts, when it's technically possible. You do not want to use -cpu host if you plan to migrate, another safer CPU type should be used then (the aforementioned -cpu migrate). Although preserving the boot CPU's vendor/family/

[PATCH 3/4] ignore PCI ECS I/O enablement

Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore write and read attempts. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |3 +++ 1 files changed, 3 inser

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Andre Przywara wrote: Avi Kivity wrote: --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct -0 /* Reserved, XSAVE, OSXSAVE */; +0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR); I think this should be handled in qemu, since

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Avi Kivity wrote: On 06/24/2009 01:44 PM, Andre Przywara wrote: Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644 --- a/arch/x86/kvm/x86.c +++ b

Re: [PATCH 2/2] introduce -cpu host target

Avi Kivity wrote: On 06/23/2009 12:47 AM, Andre Przywara wrote: Should we ignore unhandled MSRs like QEMU or Xen do? Ignoring unhandled msrs is dangerous. If a write has some effect the guest depends on, and we're not emulating that effect, the guest will fail. Similarly if you

[PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7 @@ static void do_cpuid_ent

[PATCH 3/4] ignore PCI ECS I/O enablement

Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore this write attempt. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 ++ 1 files changed, 2 insertions(

[PATCH 2/4] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 1/2 v2] allow hypervisor CPUID bit to be overriden

disable it by using: -cpu qemu64,-hypervisor Fix some whitespace damage on the way. Signed-off-by: Andre Przywara --- target-i386/helper.c | 23 +++ 1 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 8a76abd

[PATCH 2/2] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 1/2] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 2/2] introduce -cpu host target

27;, which will propagate the host's CPUID bits to the guest. Problematic bits can still be turned off by using the existing syntax (-cpu host,-skinit) Signed-off-by: Andre Przywara --- target-i386/helper.c | 65 + 1 files changed, 59 insertions(+

[PATCH 1/2] allow hypervisor CPUID bit to be overriden

. Signed-off-by: Andre Przywara --- target-i386/helper.c | 25 + 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 8a76abd..529f962 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -44,7 +44,7

[PATCH] fix renamed MSR_K8_HWCR name

The definition of MSR_K8_HWCR was removed upstream in favor of MSR_K7_HWCR. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index c283201..481010c 100644 --- a/arch/x86/kvm

[PATCH 6/6 v2] add sysexit emulation

Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara

[PATCH 5/6 v2] add sysenter emulation

Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 4/6 v2] add syscall emulation

Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. Signed-off-by: Christoph Egger Signed-off-by: Andre Przywara

Re: [PATCH 4/6] add syscall emulation

Avi Kivity wrote: On 06/17/2009 04:50 PM, Andre Przywara wrote: +static inline void +setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, +struct kvm_segment *cs, struct kvm_segment *ss) +{ +memset(cs, 0, sizeof(struct kvm_segment)); +kvm_x86_ops->get_segment(ctxt->vc

[PATCH 6/6] add sysexit emulation

Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara

[PATCH 4/6] add syscall emulation

Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. Signed-off-by: Christoph Egger Signed-off-by: Andre Przywara

[PATCH 5/6] add sysenter emulation

Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 3/6] prepare for emulation of syscall instructions

Add the flags needed for syscall, sysenter and sysexit to the opcode table. Catch (but for now ignore) the opcodes in the emulation switch/case. Signed-off-by: Andre Przywara Signed-off-by: Amit Shah Signed-off-by: Christoph Egger --- arch/x86/kvm/x86_emulate.c | 17 +++-- 1

[PATCH 2/6] add missing EFLAGS bit definitions

Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm/x86_emulate.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 22c765d..e387c83 100644 --- a/arch/x86

[PATCH 1/6] allow emulation of syscalls instructions on #UD

Add the opcodes for syscall, sysenter and sysexit to the list of instructions handled by the undefined opcode handler. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 33 ++--- 1 files changed, 26

[PATCH 0/6] add sysenter/syscall emulation for 32bit compat mode

Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. This has been tested with GE

Re: [PATCH] add sysenter/syscall emulation for 32bit compat mode

Amit Shah wrote: Hi Andre, On (Tue) Jun 16 2009 [15:25:13], Andre Przywara wrote: sysenter/sysexit are not supported on AMD's 32bit compat mode, whereas syscall is not supported on Intel's 32bit compat mode. To allow cross vendor migration we emulate the missing instructions by sett

[PATCH] add sysenter/syscall emulation for 32bit compat mode

Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-off-by: Amit Shah Sig

[PATCH] move performance counter MSR access interception to generic x86 KVM path

something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 16 arch/x86/kvm/vmx.c | 12 arch/x86/kvm/

Re: [PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

ode out of the switch and into separate functions. Ok, will do. Thanks for the review! Renewed patch will follow. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord..

[PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

y sketched by Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-of

[PATCH 1/2] use explicit 64bit storage for sysenter values

Since AMD does not support sysenter in 64bit mode, the VMCB fields storing the MSRs are truncated to 32bit upon VMRUN/#VMEXIT. So store the values in a separate 64bit storage to avoid truncation. Signed-off-by: Christoph Egger --- arch/x86/kvm/kvm_svm.h |4 arch/x86/kvm/svm.c | 12

[PATCH] allow CPUID vendor override

KVM will always report the vendor ID of the physical CPU it is running on. Allow to override this if explicitly requested on the command line. It will not suffice to name a CPU type (like -cpu phenom), but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD Signed-off-by: Andre

[PATCH 2/2] Fix cross vendor migration issue in segment segment descriptor

On AMD CPUs sometimes the DB bit in the stack segment descriptor is left as 1, although the whole segment has been made unusable. Clear it here to pass an Intel VMX entry check when cross vendor migrating. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |9 + 1 files changed, 9

[PATCH 1/2] Fix cross vendor migration issue with unusable bit

AMDs VMCB does not have an explicit unusable segment descriptor field, so we emulate it by using "not present". This has to be setup before the fixups, because this field is used there. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |7 +-- 1 files changed, 5 insert

[PATCH] [resend] set accessed bit for VMCB segment selectors

this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 23 +-- 1 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 22e88a4..dc5d88f 100644 --- a/arch/x86/kvm

Re: Running KVM on a Laptop

SVM: and containing "np"). There are no known BIOS restrictions regarding to NPT nor the BIOS needs to handle NPT in a special way. 3. If you're running KVM on your laptop, could you share the information? Does your laptop's BIOS support AMD-V or VT-x? We use hardware virtua

Re: Fast/Quiet Boot

side of the game and qemu/hw/fw_cfg.[ch] for the QEMU interface side (functions here are prefixed with fw_cfg_). So define a new channel and send your data over. Be sure to consider qemu-devel if you want to send patches. Hope that helps, Andre. -- Andre Przywara AMD-Operating System Rese

[PATCH] kvm: set accessed bit for VMCB segment selectors

In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara Acked-By: Amit Shah --- arch

[PATCH] set accessed bit for VMCB segment selectors

In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 22

Re: [PATCH] qemu: fix configuring kvm probe when using --kerneldir

;i386" -o "$cpu" = "x86_64" \) \ + -a -d "$kerneldir/arch/x86/include" ; then +kvm_cflags="$kvm_cflags -I$kerneldir/arch/x86/include" +elif test -d "$kerneldir/arch/$cpu/include" ; then +kvm_cflags="$kvm_cflags -I$ke

[PATCH] kvm: always set accessed bit in VMCS segment selectors

one. If someone has an explanation which justifies a move, I am happy to do this. Signed-off-by: Andre Przywara --- arch/x86/kvm/vmx.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 9b56d21..d19e39c 100644 --- a/arch/x86

[PATCH] KVM-userspace: allow CPUID vendor override

Hi, currently KVM always propagates the host CPU vendor ID to the guest. This patch allows to override this behavior by explicitly specifying a vendor ID with -cpu qemu64,vendor=KVMKVMKVMKVM. This proved to be useful for cross vendor migration tests. Regards, Andre. Andre Przywara AMD-Operating

Re: [PATCH] CPUID Masking MSRs

this code shows almost everything you probably need: http://xenbits.xensource.com/xen-unstable.hg?rev/be20b11656bb Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: Advanced Mic

[PATCH] kvm-userspace: Fix a compiler warning

The following small patch fixes a compiler warning in KVM's vl.c Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> --- diff --git a/qemu/vl.c b/qemu/vl.c index 7b58605..b489acd 100644 --- a/qemu/vl.c +++ b/qemu/vl.c @@ -4611,7 +4611,7 @@ static int gethugepagesize(void) {

Re: [PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

view and apply all of the first patches. We can continue to discuss the last patch independently of the first three if needed. Sounds like a plan. I will start with this and hope for some advice on the BOCHS BIOS issue. Thanks for your ideas! Regards, Andre. Andre Przywara wrote:

[PATCH 3/3] v2: KVM-userspace: generate a SRAT table to describe the guests NUMA topology

. Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company & Co. KG, Wilschdorfer Landstr. 101, 01109 Dresde

[PATCH 2/3] v2: KVM-userspace: allocate guest resources from different host nodes

emory actually faults in). The presence of libnuma will be auto-detected. Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Sax

[PATCH 1/3] v2: KVM-userspace: introduce -numa command line option

The attached patch parses the command line options given at -numa and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to s

[PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

st nodes, a possible command line looks like: -numa 3,mem:1024M;512M;512M,cpu:0-1;2;3 Please note that you have to quote the semicolons on the shell. The monitor command is left out for now and will be send later. Please apply. Regards, Andre. Signed-off-by: Andre Przywara <[EMAIL PROTECTED]

Re: [PATCH 0/3] KVM-userspace: add NUMA support for guests

Avi Kivity wrote: Andre Przywara wrote: The user (or better: management application) specifies the host nodes the guest should use: -nodes 2,3 would create a two node guest mapped to node 2 and 3 on the host. These numbers are handed over to libnuma: VCPUs are pinned to the nodes and the

[PATCH 3/3] KVM-userspace: generate a SRAT table to describe the guests NUMA topology

: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company & Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany Regi

[PATCH 2/3] KVM-userspace: allocate guest resources from different host nodes

emory actually faults in). Since libnuma is not that widespread (in default installations), I chose 'enable via configure' by now: --enable-numa will compile the parts in. Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OS

[PATCH 1/3] KVM-userspace: introduce -nodes command line option

The attached patch parses a list of host nodes given on the command line and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to s

[PATCH 0/3] KVM-userspace: add NUMA support for guests

tch 3/3: generate an appropriate SRAT ACPI table Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company & Co.

[PATCH] x86 CPUID extended family/model

qemu64,family=16,model=4,stepping=2 Attached patch introduces support for specifying those bits on the command line and passing them to the guest. (Patch applies against qemu-svn and kvm-userspace) Signed-off-by: Andre Przywara <[EMAIL PROTECTED]> Regards, Andre. P.S. I heard of a

<    2   3   4   5   6   7