On Mon, Mar 23, 2015 at 12:05 PM, Alex Bennée alex.ben...@linaro.org wrote:
From: Peter Maydell peter.mayd...@linaro.org
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env-banked_spsr[1]
.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.0
Otherwise...
Reviewed-by: Greg Bellows greg.bell...@linaro.org
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On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée alex.ben...@linaro.org wrote:
For migration to work we need to sync all of the register state. This is
especially noticeable when GCC starts using FP registers as spill
registers even with integer programs.
Signed-off-by: Alex Bennée
On Mon, Mar 9, 2015 at 8:26 AM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Wed, Mar 04, 2015 at 02:35:52PM +, Alex Bennée wrote:
From: Christoffer Dall christoffer.d...@linaro.org
The current code was negatively indexing the cpu state array and not
synchronizing banked spsr
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée alex.ben...@linaro.org wrote:
While observing KVM traces I can see additional IRQ calls on pretty much
every MMIO access which is just plain inefficient. Only update the QEMU
IRQ level if something has actually changed from last time. Otherwise we
, translate_priority);
--
2.3.1
Reviewed-by: Greg Bellows greg.bell...@linaro.org
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