[PATCH v2 1/2] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

. On systems with two threads per core this patch halves the size of the lpid pool that the allocator sees and use two lpids per VM. Use even numbers to speedup vcpu lpid computation with consecutive lpids per VM: vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on. Signed-off-by: Mihai Caraman

[PATCH v2 2/2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec and hardware thread support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - new patch arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm

[PATCH] KVM: PPC: Remove shared defines for SPE and AltiVec interrupts

We currently decide at compile-time which of the SPE or AltiVec units to support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and CONFIG_PPC_E500MC and remove shared defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/kvm_asm.h | 20

[PATCH] KVM: PPC: Remove the tasklet used by the hrtimer

Powerpc timer implementation is a copycat version of s390. Now that they removed the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this optimization. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com

[PATCH v2 1/2] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

. On systems with two threads per core this patch halves the size of the lpid pool that the allocator sees and use two lpids per VM. Use even numbers to speedup vcpu lpid computation with consecutive lpids per VM: vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on. Signed-off-by: Mihai Caraman

[PATCH v2 2/2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec and hardware thread support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - new patch arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm

[PATCH] KVM: PPC: Remove shared defines for SPE and AltiVec interrupts

We currently decide at compile-time which of the SPE or AltiVec units to support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and CONFIG_PPC_E500MC and remove shared defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/kvm_asm.h | 20

[PATCH] KVM: PPC: Remove the tasklet used by the hrtimer

Powerpc timer implementation is a copycat version of s390. Now that they removed the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this optimization. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com

[PATCH 1/2] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

with two threads per core this patch halves the size of the lpid pool that the allocator sees and use two lpids per VM. Use even numbers to speedup vcpu lpid computation with consecutive lpids per VM: vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on. Signed-off-by: Mihai Caraman mihai.cara

[PATCH 2/2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec and hardware threading support are in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index

[PATCH 2/2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec and hardware threading support are in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index

[PATCH v4 4/6] KVM: PPC: Move ONE_REG AltiVec support to powerpc

Move ONE_REG AltiVec support to powerpc generic layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG AltiVec support powerpc generic v2: - add comment describing VCSR register representation in KVM vs

[PATCH v4 6/6] KVM: PPC: Booke: Add ONE_REG support for IVPR and IVORs

Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15 and 35 in booke common layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - add ONE_REG IVPR - use IVPR, IVOR2 and IVOR8 setters - add api documentation for ONE_REG IVPR and IVORs v3: - new

[PATCH v4 0/6] KVM: PPC: Book3e: AltiVec support

into account feedback Mihai Caraman (6): KVM: PPC: Book3E: Increase FPU laziness KVM: PPC: Book3e: Add AltiVec support KVM: PPC: Make ONE_REG powerpc generic KVM: PPC: Move ONE_REG AltiVec support to powerpc KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation KVM: PPC

[PATCH v4 3/6] KVM: PPC: Make ONE_REG powerpc generic

Make ONE_REG generic for server and embedded architectures by moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG

[PATCH v4 2/6] KVM: PPC: Book3e: Add AltiVec support

AltiVec, so we always need to support AltiVec in KVM and implicitly in host to reflect interrupts and to save/restore the unit context. KVM will be loaded on cores with AltiVec unit only if CONFIG_ALTIVEC is defined. Use this define to guard KVM AltiVec logic. Signed-off-by: Mihai Caraman mihai.cara

[PATCH v4 5/6] KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation

Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation for ONE_REG support. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - new patch - add api documentation for ONE_REG IVPR and IVORs arch/powerpc/kvm/booke.c | 24 arch

[PATCH v4 1/6] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by loading the guest state into the unit before entering the guest instead of doing it on each vcpu schedule. Without this improvement an interrupt may claim floating point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - update

[PATCH v2 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai

[PATCH v2 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

readability especially in KVM. Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting c58ce397 and 6b310fc5 patches that added common defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: Alexander Graf ag...@suse.de --- arch

[PATCH v4 0/6] KVM: PPC: Book3e: AltiVec support

into account feedback Mihai Caraman (6): KVM: PPC: Book3E: Increase FPU laziness KVM: PPC: Book3e: Add AltiVec support KVM: PPC: Make ONE_REG powerpc generic KVM: PPC: Move ONE_REG AltiVec support to powerpc KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation KVM: PPC

[PATCH v4 6/6] KVM: PPC: Booke: Add ONE_REG support for IVPR and IVORs

Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15 and 35 in booke common layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - add ONE_REG IVPR - use IVPR, IVOR2 and IVOR8 setters - add api documentation for ONE_REG IVPR and IVORs v3: - new

[PATCH v4 3/6] KVM: PPC: Make ONE_REG powerpc generic

Make ONE_REG generic for server and embedded architectures by moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG

[PATCH v4 4/6] KVM: PPC: Move ONE_REG AltiVec support to powerpc

Move ONE_REG AltiVec support to powerpc generic layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG AltiVec support powerpc generic v2: - add comment describing VCSR register representation in KVM vs

[PATCH v4 2/6] KVM: PPC: Book3e: Add AltiVec support

AltiVec, so we always need to support AltiVec in KVM and implicitly in host to reflect interrupts and to save/restore the unit context. KVM will be loaded on cores with AltiVec unit only if CONFIG_ALTIVEC is defined. Use this define to guard KVM AltiVec logic. Signed-off-by: Mihai Caraman mihai.cara

[PATCH v4 1/6] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by loading the guest state into the unit before entering the guest instead of doing it on each vcpu schedule. Without this improvement an interrupt may claim floating point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - update

[PATCH v4 5/6] KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation

Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation for ONE_REG support. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - new patch - add api documentation for ONE_REG IVPR and IVORs arch/powerpc/kvm/booke.c | 24 arch

[PATCH] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

moves lpid to vcpu level and allocates a pool of lpids (equal to the number of threads per core) per VM. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- Please rebase this patch before [PATCH v3 5/5] KVM: PPC: Book3E: Enable e6500 core to proper handle SMP guests. arch/powerpc

[PATCH 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

Though SPE/AltiVec shares interrupts numbers on BookE cores, use distinct defines to identify these numbers. This improves code readability especially in KVM. Revert c58ce397 and 6b310fc5 patches that added common defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch

[PATCH 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai

[PATCH] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

moves lpid to vcpu level and allocates a pool of lpids (equal to the number of threads per core) per VM. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- Please rebase this patch before [PATCH v3 5/5] KVM: PPC: Book3E: Enable e6500 core to proper handle SMP guests. arch/powerpc

[PATCH v3 0/5] KVM: PPC: Book3e: AltiVec support

into account feedback Mihai Caraman (5): KVM: PPC: Book3e: Increase FPU laziness KVM: PPC: Book3e: Add AltiVec support KVM: PPC: Move ONE_REG AltiVec support to powerpc KVM: PPC: Booke: Add ONE_REG IVORs support KVM: PPC: Book3e: Enable e6500 core arch/powerpc/include/uapi/asm/kvm.h | 29

[PATCH v3 2/5] KVM: PPC: Book3e: Add AltiVec support

Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - use distinct SPE/AltiVec

[PATCH v3 3/5] KVM: PPC: Move ONE_REG AltiVec support to powerpc

Make ONE_REG AltiVec support common across server and embedded implementations moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - make ONE_REG AltiVec support powerpc generic v2

[PATCH v3 5/5] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2-v3: - no changes arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index 19dd927

[PATCH v3 4/5] KVM: PPC: Booke: Add ONE_REG IVORs support

Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - new patch arch/powerpc/include/uapi/asm/kvm.h | 24 +++ arch/powerpc/kvm/booke.c| 132 arch/powerpc/kvm/e500

[PATCH v3 1/5] KVM: PPC: Book3e: Increase FPU laziness

Increase FPU laziness by calling kvmppc_load_guest_fp() just before returning to guest instead of each sched in. Without this improvement an interrupt may also claim floting point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - no changes v2: - remove

[PATCH v3 0/5] KVM: PPC: Book3e: AltiVec support

into account feedback Mihai Caraman (5): KVM: PPC: Book3e: Increase FPU laziness KVM: PPC: Book3e: Add AltiVec support KVM: PPC: Move ONE_REG AltiVec support to powerpc KVM: PPC: Booke: Add ONE_REG IVORs support KVM: PPC: Book3e: Enable e6500 core arch/powerpc/include/uapi/asm/kvm.h | 29

[PATCH v3 2/5] KVM: PPC: Book3e: Add AltiVec support

Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - use distinct SPE/AltiVec

[PATCH v3 3/5] KVM: PPC: Move ONE_REG AltiVec support to powerpc

Make ONE_REG AltiVec support common across server and embedded implementations moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - make ONE_REG AltiVec support powerpc generic v2

[PATCH v3 5/5] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2-v3: - no changes arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index 19dd927

[PATCH v3 4/5] KVM: PPC: Booke: Add ONE_REG IVORs support

Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - new patch arch/powerpc/include/uapi/asm/kvm.h | 24 +++ arch/powerpc/kvm/booke.c| 132 arch/powerpc/kvm/e500

[PATCH v3 1/5] KVM: PPC: Book3e: Increase FPU laziness

Increase FPU laziness by calling kvmppc_load_guest_fp() just before returning to guest instead of each sched in. Without this improvement an interrupt may also claim floting point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v3: - no changes v2: - remove

[PATCH v6 0/5] Read guest last instruction from kvmppc_get_last_inst()

exception handled in the host and the TODO for execute-but-not-read entries and TLB eviction. Mihai Caraman (5): KVM: PPC: e500mc: Revert add load inst fixup KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 KVM: PPC: Book3s: Remove kvmppc_read_inst() function KVM: PPC: Alow

[PATCH v6 1/5] KVM: PPC: e500mc: Revert add load inst fixup

the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit add load inst fixup. lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v6-v2

[PATCH v6 2/5] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1

Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v6-v2: - no change arch/powerpc/include/asm/mmu-book3e.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/mmu

[PATCH v6 5/5] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation

the interrupt vector from host. This imposes additional synchronizations for cores like FSL e6500 that shares host IVOR registers between hardware threads. This optimized solution can be later developed on top of this patch. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v6: - no change v5

[PATCH v6 3/5] KVM: PPC: Book3s: Remove kvmppc_read_inst() function

. With an error returning kvmppc_get_last_inst we can just use completely get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead. As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld() instead. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v6

[PATCH v6 4/5] KVM: PPC: Alow kvmppc_get_last_inst() to fail

-by: Mihai Caraman mihai.cara...@freescale.com --- v6: - rewrite kvmppc_get_last_inst() swap code to be understood at a glimpse :) - use inst in kvmppc_load_last_inst - these changes compile on book3s, please validate the functionality and do the necessary changes! v5: - don't swap when load

[PATCH v6 0/5] Read guest last instruction from kvmppc_get_last_inst()

exception handled in the host and the TODO for execute-but-not-read entries and TLB eviction. Mihai Caraman (5): KVM: PPC: e500mc: Revert add load inst fixup KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 KVM: PPC: Book3s: Remove kvmppc_read_inst() function KVM: PPC: Alow

[PATCH v6 4/5] KVM: PPC: Alow kvmppc_get_last_inst() to fail

-by: Mihai Caraman mihai.cara...@freescale.com --- v6: - rewrite kvmppc_get_last_inst() swap code to be understood at a glimpse :) - use inst in kvmppc_load_last_inst - these changes compile on book3s, please validate the functionality and do the necessary changes! v5: - don't swap when load

[PATCH v6 5/5] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation

the interrupt vector from host. This imposes additional synchronizations for cores like FSL e6500 that shares host IVOR registers between hardware threads. This optimized solution can be later developed on top of this patch. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v6: - no change v5

[PATCH v5 1/5] KVM: PPC: e500mc: Revert add load inst fixup

the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit add load inst fixup. lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5-v2

[PATCH v5 5/5] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation

the interrupt vector from host. This imposes additional synchronizations for cores like FSL e6500 that shares host IVOR registers between hardware threads. This optimized solution can be later developed on top of this patch. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5: - return

[PATCH v5 0/5] Read guest last instruction from kvmppc_get_last_inst()

exception handled in the host and the TODO for execute-but-not-read entries and TLB eviction. Mihai Caraman (5): KVM: PPC: e500mc: Revert add load inst fixup KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 KVM: PPC: Book3s: Remove kvmppc_read_inst() function KVM: PPC: Alow

[PATCH v5 3/5] KVM: PPC: Book3s: Remove kvmppc_read_inst() function

. With an error returning kvmppc_get_last_inst we can just use completely get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead. As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld() instead. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5

[PATCH v5 4/5] KVM: PPC: Alow kvmppc_get_last_inst() to fail

-by: Mihai Caraman mihai.cara...@freescale.com --- v5 - don't swap when load fail - convert the return value space of kvmppc_ld() v4: - these changes compile on book3s, please validate the functionality and do the necessary adaptations! - common declaration and enum for kvmppc_load_last_inst

[PATCH v5 2/5] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1

Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5-v2: - no change arch/powerpc/include/asm/mmu-book3e.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/mmu

[PATCH v5 4/5] KVM: PPC: Alow kvmppc_get_last_inst() to fail

-by: Mihai Caraman mihai.cara...@freescale.com --- v5 - don't swap when load fail - convert the return value space of kvmppc_ld() v4: - these changes compile on book3s, please validate the functionality and do the necessary adaptations! - common declaration and enum for kvmppc_load_last_inst

[PATCH v5 1/5] KVM: PPC: e500mc: Revert add load inst fixup

the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit add load inst fixup. lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5-v2

[PATCH v5 3/5] KVM: PPC: Book3s: Remove kvmppc_read_inst() function

. With an error returning kvmppc_get_last_inst we can just use completely get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead. As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld() instead. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5

[PATCH v5 0/5] Read guest last instruction from kvmppc_get_last_inst()

exception handled in the host and the TODO for execute-but-not-read entries and TLB eviction. Mihai Caraman (5): KVM: PPC: e500mc: Revert add load inst fixup KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 KVM: PPC: Book3s: Remove kvmppc_read_inst() function KVM: PPC: Alow

[PATCH v5 5/5] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation

the interrupt vector from host. This imposes additional synchronizations for cores like FSL e6500 that shares host IVOR registers between hardware threads. This optimized solution can be later developed on top of this patch. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5: - return

[PATCH v5 2/5] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1

Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v5-v2: - no change arch/powerpc/include/asm/mmu-book3e.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/mmu

[PATCH v2] KVM: PPC: e500: Emulate power management control SPR

guest request as a general store. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - treat the operation as a general store arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/e500_emulate.c | 12 2 files changed, 13 insertions(+) diff --git a/arch/powerpc

[PATCH v2] KVM: PPC: e500: Emulate power management control SPR

guest request as a general store. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - treat the operation as a general store arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/e500_emulate.c | 12 2 files changed, 13 insertions(+) diff --git a/arch/powerpc

[RFC PATCH 1/4] powerpc/booke64: Add LRAT next and max entries to tlb_core_data structure

LRAT (Logical to Real Address Translation) is shared between hw threads. Add LRAT next and max entries to tlb_core_data structure and initialize them. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/mmu-book3e.h | 7 +++ arch/powerpc/include/asm

[RFC PATCH 3/4] KVM: PPC: e500: TLB emulation for IND entries

is not available just invalidate guest's ea and report a tlbsx miss. This patch only implements the invalidation and let a TODO note for searching HW TLB0. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/mmu-book3e.h | 2 + arch/powerpc/kvm/e500.h | 81

[RFC PATCH 0/4] KVM Book3E support for HTW guests

KVM Book3E support for Hardware Page Tablewalk enabled guests. Mihai Caraman (4): powerpc/booke64: Add LRAT next and max entries to tlb_core_data structure KVM: PPC: Book3E: Handle LRAT error exception KVM: PPC: e500: TLB emulation for IND entries KVM: PPC: e500mc: Advertise E.PT

[RFC PATCH 4/4] KVM: PPC: e500mc: Advertise E.PT to support HTW guests

Enable E.PT for vcpus with MMU MAV 2.0 to support Hardware Page Tablewalk (HTW) in guests. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500_mmu.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc

[RFC PATCH 2/4] KVM: PPC: Book3E: Handle LRAT error exception

Handle LRAT error exception with support for lrat mapping and invalidation. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/include/asm/kvm_ppc.h| 2 + arch/powerpc/include/asm/mmu-book3e.h | 3 + arch/powerpc

[RFC PATCH 0/4] KVM Book3E support for HTW guests

KVM Book3E support for Hardware Page Tablewalk enabled guests. Mihai Caraman (4): powerpc/booke64: Add LRAT next and max entries to tlb_core_data structure KVM: PPC: Book3E: Handle LRAT error exception KVM: PPC: e500: TLB emulation for IND entries KVM: PPC: e500mc: Advertise E.PT

[RFC PATCH 1/4] powerpc/booke64: Add LRAT next and max entries to tlb_core_data structure

LRAT (Logical to Real Address Translation) is shared between hw threads. Add LRAT next and max entries to tlb_core_data structure and initialize them. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/mmu-book3e.h | 7 +++ arch/powerpc/include/asm

[RFC PATCH 3/4] KVM: PPC: e500: TLB emulation for IND entries

is not available just invalidate guest's ea and report a tlbsx miss. This patch only implements the invalidation and let a TODO note for searching HW TLB0. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/mmu-book3e.h | 2 + arch/powerpc/kvm/e500.h | 81

[RFC PATCH 2/4] KVM: PPC: Book3E: Handle LRAT error exception

Handle LRAT error exception with support for lrat mapping and invalidation. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/include/asm/kvm_ppc.h| 2 + arch/powerpc/include/asm/mmu-book3e.h | 3 + arch/powerpc

[RFC PATCH 4/4] KVM: PPC: e500mc: Advertise E.PT to support HTW guests

Enable E.PT for vcpus with MMU MAV 2.0 to support Hardware Page Tablewalk (HTW) in guests. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500_mmu.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc

[PATCH] KVM: PPC: e500: Fix default tlb for victim hint

Tlb search operation used for victim hint relies on the default tlb set by the host. When hardware tablewalk support is enabled in the host, the default tlb is TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb when searching for victim hint. Signed-off-by: Mihai

[PATCH] KVM: PPC: e500: Emulate power management control SPR

guest request as nop. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500_emulate.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 002d517..98a22e5 100644 --- a/arch/powerpc/kvm

[PATCH 6/6 v2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - no changes arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index c60b653

[PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVec support

Add ONE_REG support for AltiVec on Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - add comment describing VCSR register representation in KVM vs kernel arch/powerpc/include/uapi/asm/kvm.h | 5 + arch/powerpc/kvm/booke.c| 34

[PATCH 2/6 v2] KVM: PPC: Book3E: Refactor SPE/FP exit handling

-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - enable SPE only if !HV SPE arch/powerpc/kvm/booke.c | 93 +++- 1 file changed, 60 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 3c86d9b..80cd8df

[PATCH 4/6 v2] KVM: PPC: Book3E: Add AltiVec support

Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - integrate Paul's FP/VMX/VSX changes arch/powerpc/kvm/booke.c | 67

[PATCH 1/6 v2] KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers

Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec which share the same interrupt numbers. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - remove outdated definitions arch/powerpc/include/asm/kvm_asm.h| 8 arch/powerpc/kvm/booke.c

[PATCH 0/6 v2] KVM: PPC: Book3e: AltiVec support

Add KVM Book3E AltiVec support and enable e6500 core. Integrates Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue in January and take into account feedback. Mihai Caraman (6): KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers KVM: PPC: Book3E: Refactor SPE/FP exit

[PATCH 3/6 v2] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by calling kvmppc_load_guest_fp() just before returning to guest instead of each sched in. Without this improvement an interrupt may also claim floting point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - remove fpu_active - add

[PATCH] KVM: PPC: e500: Fix default tlb for victim hint

Tlb search operation used for victim hint relies on the default tlb set by the host. When hardware tablewalk support is enabled in the host, the default tlb is TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb when searching for victim hint. Signed-off-by: Mihai

[PATCH] KVM: PPC: e500: Emulate power management control SPR

guest request as nop. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- arch/powerpc/kvm/e500_emulate.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 002d517..98a22e5 100644 --- a/arch/powerpc/kvm

[PATCH 6/6 v2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - no changes arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index c60b653

[PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVec support

Add ONE_REG support for AltiVec on Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - add comment describing VCSR register representation in KVM vs kernel arch/powerpc/include/uapi/asm/kvm.h | 5 + arch/powerpc/kvm/booke.c| 34

[PATCH 2/6 v2] KVM: PPC: Book3E: Refactor SPE/FP exit handling

-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - enable SPE only if !HV SPE arch/powerpc/kvm/booke.c | 93 +++- 1 file changed, 60 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 3c86d9b..80cd8df

[PATCH 1/6 v2] KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers

Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec which share the same interrupt numbers. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - remove outdated definitions arch/powerpc/include/asm/kvm_asm.h| 8 arch/powerpc/kvm/booke.c

[PATCH 4/6 v2] KVM: PPC: Book3E: Add AltiVec support

Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - integrate Paul's FP/VMX/VSX changes arch/powerpc/kvm/booke.c | 67

[PATCH 0/6 v2] KVM: PPC: Book3e: AltiVec support

Add KVM Book3E AltiVec support and enable e6500 core. Integrates Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue in January and take into account feedback. Mihai Caraman (6): KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers KVM: PPC: Book3E: Refactor SPE/FP exit

[PATCH 3/6 v2] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by calling kvmppc_load_guest_fp() just before returning to guest instead of each sched in. Without this improvement an interrupt may also claim floting point corrupting guest state. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v2: - remove fpu_active - add

[PATCH 1/5 v4] KVM: PPC: e500mc: Revert add load inst fixup

the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit add load inst fixup. lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4-v2

[PATCH 5/5 v4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation

vector from host. Some cores share host IVOR registers between hardware threads, which is the case of FSL e6500, which impose additional synchronization logic for this solution to work. The optimization can be addressed later on top of this patch. Signed-off-by: Mihai Caraman mihai.cara

[PATCH 3/5 v4] KVM: PPC: Book3s: Remove kvmppc_read_inst() function

. With an error returning kvmppc_get_last_inst we can just use completely get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead. As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld() instead. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4

[PATCH 2/5 v4] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1

Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com --- v4-v2: - no change arch/powerpc/include/asm/mmu-book3e.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmu

[PATCH 4/5 v4] KVM: PPC: Alow kvmppc_get_last_inst() to fail

-by: Mihai Caraman mihai.cara...@freescale.com --- v4: - these changes compile on book3s, please validate the functionality and do the necessary adaptations! - common declaration and enum for kvmppc_load_last_inst() - remove kvmppc_read_inst() in a preceding patch v3: - rework patch

[PATCH 0/5 v4] Read guest last instruction from kvmppc_get_last_inst()

exception handled in the host and the TODO for execute-but-not-read entries and TLB eviction. Mihai Caraman (5): KVM: PPC: e500mc: Revert add load inst fixup KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 KVM: PPC: Book3s: Remove kvmppc_read_inst() function KVM: PPC: Alow

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