Paolo Bonzini wrote on 2015-11-13:
> Commit 7a1638ce4220 ("nEPT: Redefine EPT-specific link_shadow_page()",
> 2013-08-05) says:
>
> Since nEPT doesn't support A/D bit, we should not set those bit
> when building the shadow page table.
> but this is not necessary. Even though nEPT doesn't
Michael S. Tsirkin wrote on 2015-11-16:
> This patch adds a new parameter: eptp_switching_test, which enables
> testing EPT switching on VMX if supported by hardware. All EPT
> entries are initialized to the same value so this adds no useful
> functionality by itself, but can be used to test
Paolo Bonzini wrote on 2015-10-01:
Hi Paolo
Sorry for the late reply. I am just back from vacation.
>
>
> On 13/04/2015 13:34, Nadav Amit wrote:
>> x86 architecture defines differences between the reset and INIT
>> sequences. INIT does not initialize the FPU (including MMX, XMM, YMM,
>>
Zhang, Yang Z wrote on 2015-08-04:
Paolo Bonzini wrote on 2015-08-04:
On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can
be inferred from the IOAPIC routes but the TMR cannot. The
hardware behavior on the other hand can
Paolo Bonzini wrote on 2015-08-04:
On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can be
inferred from the IOAPIC routes but the TMR cannot. The hardware
behavior on the other hand can be implemented purely within the LAPIC.
So
Paolo Bonzini wrote on 2015-08-03:
On 03/08/2015 12:23, Zhang, Yang Z wrote:
In any case, the TMR behavior introduced by the APICv patches is
completely different from the hardware behavior, so it has to be fixed.
But any real problem with it?
It is a problem for split irqchip, where
Paolo Bonzini wrote on 2015-08-03:
On 03/08/2015 04:37, Zhang, Yang Z wrote:
Only virtualized APIC register reads use the virtual TMR
registers (SDM
29.4.2 or 29.5), but these just read data from the corresponding
field in the virtual APIC page.
24.11.4 Software Access to Related
Paolo Bonzini wrote on 2015-07-31:
On 31/07/2015 01:26, Zhang, Yang Z wrote:
Do not compute TMR in advance. Instead, set the TMR just before
the interrupt is accepted into the IRR. This limits the coupling
between IOAPIC and LAPIC.
Uh.., it back to original way which is wrong. You
Paolo Bonzini wrote on 2015-07-31:
On 31/07/2015 04:49, Steve Rutherford wrote:
Oh... Yeah. That's a damn good point, given that the interrupt can be
injected from another thread while one is in that guest vcpu.
Easiest time to update the TMR should be on guest entry through
Paolo Bonzini wrote on 2015-07-29:
Do not compute TMR in advance. Instead, set the TMR just before the
interrupt is accepted into the IRR. This limits the coupling between
IOAPIC and LAPIC.
Uh.., it back to original way which is wrong. You cannot modify the apic
page(here is the TMR reg)
Paolo Bonzini wrote on 2015-04-24:
On 24/04/2015 09:46, Zhang, Yang Z wrote:
On the other hand vmexit is lighter and lighter on newer
processors; a Sandy Bridge has less than half the vmexit cost of a
Core 2 (IIRC
1000 vs. 2500 clock cycles approximately).
1000 cycles? I remember
Paolo Bonzini wrote on 2015-04-24:
On 24/04/2015 03:16, Zhang, Yang Z wrote:
This is interesting since previous measurements on KVM have had the
exact opposite results. I think we need to understand this a lot
more.
What I can tell is that vmexit is heavy. So it is reasonable to see
H. Peter Anvin wrote on 2015-04-24:
On 04/23/2015 08:28 AM, Dave Hansen wrote:
On 04/23/2015 02:13 PM, Liang Li wrote:
When compiling kernel on westmere, the performance of eager FPU is
about 0.4% faster than lazy FPU.
Do you have an theory why this is? What does the regression come from?
Paolo Bonzini wrote on 2015-02-03:
On 02/02/2015 16:33, Wincy Van wrote:
static void vmx_accomp_nested_posted_intr(struct kvm_vcpu *vcpu) {
struct vcpu_vmx *vmx = to_vmx(vcpu);
if (is_guest_mode(vcpu)
vmx-nested.posted_intr_nv != -1
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
@@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
(unsigned long
*)__get_free_page(GFP_KERNEL);
if (!vmx_msr_bitmap_longmode_x2apic
Zhang, Yang Z wrote on 2015-01-28:
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should only
Wincy Van wrote on 2015-01-24:
Currently, if L1 enables MSR_BITMAP, we will emulate this feature, all of L2's
msr access is intercepted by L0. Since many features like virtualize x2apic
mode
has a complicated logic and it is difficult for us to emulate, we should use
hardware and merge the
Zhang, Yang Z wrote on 2015-01-28:
Wincy Van wrote on 2015-01-24:
When L2 is using x2apic, we can use virtualize x2apic mode to gain
higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls for the
nested apicv patches.
Sorry, replied
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should only be loaded in non-nested entry
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
You are right, but this is not fit for all the cases, we should
custom the nested_msr_bitmap.
e.g. Currently L0 wants to intercept some of the x2apic msrs' reading
Wincy Van wrote on 2015-01-24:
When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls for the nested
apicv patches.
Signed-off-by: Wincy Van fanwenyi0...@gmail.com
---
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls
Wincy Van wrote on 2015-01-28:
When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls for the nested
apicv patches.
Signed-off-by: Wincy Van fanwenyi0...@gmail.com
---
Wincy Van wrote on 2015-01-29:
On Thu, Jan 29, 2015 at 10:54 AM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
-8646,7 +8750,8 @@ static void prepare_vmcs02(struct kvm_vcpu
*vcpu, struct vmcs12 *vmcs12)
else
vmcs_write64(APIC_ACCESS_ADDR,
page_to_phys(vmx
Wincy Van wrote on 2015-01-28:
v1 --- v2:
Use spin lock to ensure vmcs12 is safe when doing nested
posted interrupt delivery.
v2 --- v3:
1. Add a new field in nested_vmx to avoid the spin lock in v2.
2. Drop send eoi to L1 when doing nested interrupt delivery.
3. Use hardware MSR
Wincy Van wrote on 2015-01-16:
To enable nested apicv support, we need per-cpu vmx control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in the
nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
Wincy Van wrote on 2015-01-21:
On Wed, Jan 21, 2015 at 4:07 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
+ if (vector == vmcs12-posted_intr_nv +
nested_cpu_has_posted_intr(vmcs12)) { + if (vcpu-mode
== IN_GUEST_MODE) + apic-send_IPI_mask(get_cpu_mask(vcpu-cpu
Wincy Van wrote on 2015-01-20:
If vcpu has a interrupt in vmx non-root mode, we will kick that vcpu
to inject interrupt timely. With posted interrupt processing, the kick
intr is not needed, and interrupts are fully taken care of by hardware.
In nested vmx, this feature avoids much more
Wincy Van wrote on 2015-01-16:
When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
performance.
This patch also introduces nested_vmx_check_apicv_controls for the nested
apicv patches.
Signed-off-by: Wincy Van fanwenyi0...@gmail.com
To enable x2apic, should you to
Wincy Van wrote on 2015-01-20:
Hi, Yang,
Could you please have a look at this patch set?
Your comment is very appreciated!
Sure. I will take a look.
Thanks,
Wincy
Best regards,
Yang
Paolo Bonzini wrote on 2014-12-23:
On 23/12/2014 10:07, Wu, Feng wrote:
On 23/12/2014 01:37, Zhang, Yang Z wrote:
I don't quite understand it. If user set an interrupt's affinity
to a CPU, but he still see the interrupt delivers to other CPUs in host.
Do you think it is a right behavior
Jiang Liu wrote on 2014-12-24:
On 2014/12/24 9:38, Zhang, Yang Z wrote:
Paolo Bonzini wrote on 2014-12-23:
On 23/12/2014 10:07, Wu, Feng wrote:
On 23/12/2014 01:37, Zhang, Yang Z wrote:
I don't quite understand it. If user set an interrupt's affinity
to a CPU, but he still see
Wu, Feng wrote on 2014-12-24:
Zhang, Yang Z wrote on 2014-12-24:
Cc: io...@lists.linux-foundation.org; linux-ker...@vger.kernel.org;
KVM list; Eric Auger
Subject: RE: [v3 06/26] iommu, x86: No need to migrating irq for
VT-d Posted-Interrupts
Jiang Liu wrote on 2014-12-24:
On 2014/12
Paolo Bonzini wrote on 2014-12-19:
On 19/12/2014 02:46, Zhang, Yang Z wrote:
If the IRQ is posted, its affinity is controlled by guest (irq
--- vCPU pCPU), it has no effect when host changes its affinity.
That's the problem: User is able to changes it in host but it never
takes
Paolo Bonzini wrote on 2014-12-23:
The problem is we still need to support PI with lowest priority
delivery mode
even if guest does not configure irq affinity via /proc/irq/. Don't we?
Yes, but we can get the basic support working first.
I and Feng talked on irc and agreed to start with a
Feng Wu wrote on 2014-12-12:
We don't need to migrate the irqs for VT-d Posted-Interrupts here.
When 'pst' is set in IRTE, the associated irq will be posted to guests
instead of interrupt remapping. The destination of the interrupt is
set in Posted-Interrupts Descriptor, and the migration
Feng Wu wrote on 2014-12-12:
This patch defines a new interface kvm_find_dest_vcpu for
VT-d PI, which can returns the destination vCPU of the
interrupt for guests.
Since VT-d PI cannot handle broadcast/multicast interrupt,
Here we only handle Fixed and Lowest priority interrupts.
The
Feng Wu wrote on 2014-12-12:
Currently, we use a global vector as the Posted-Interrupts
Notification Event for all the vCPUs in the system. We need to
introduce another global vector for VT-d Posted-Interrtups, which will
be used to wakeup the sleep vCPU when an external interrupt from a
Paolo Bonzini wrote on 2014-12-18:
On 18/12/2014 04:14, Wu, Feng wrote:
linux-kernel-ow...@vger.kernel.org wrote on
mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Paolo:
x...@kernel.org; Gleb Natapov; Paolo Bonzini; dw...@infradead.org;
Feng Wu wrote on 2014-12-12:
This patch initializes the VT-d Posted-Interrupts Descriptor.
Signed-off-by: Feng Wu feng...@intel.com
---
arch/x86/kvm/vmx.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index
Paolo Bonzini wrote on 2014-12-19:
On 18/12/2014 15:49, Zhang, Yang Z wrote:
Here, we introduce a similar way with 'apic_arb_prio' to handle
guest lowest priority interrtups when VT-d PI is used. Here is the
ideas: - Each vCPU has a counter 'round_robin_counter'. - When
guests sets
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-18:
jiang@linux.intel.com
Cc: eric.au...@linaro.org; linux-ker...@vger.kernel.org;
io...@lists.linux-foundation.org; kvm@vger.kernel.org; Wu, Feng
Subject: RE: [v3 06/26] iommu, x86: No need to migrating irq for
VT-d Posted
On 18/12/2014 15:49, Zhang, Yang Z wrote:
Here, we introduce a similar way with 'apic_arb_prio' to handle
guest lowest priority interrtups when VT-d PI is used. Here is
the
ideas: - Each vCPU has a counter 'round_robin_counter'. - When
guests sets an interrupts to lowest priority, we
Wu, Feng wrote on 2014-12-19:
iommu-boun...@lists.linux-foundation.org wrote on
mailto:iommu-boun...@lists.linux-foundation.org] On Behalf Of:
Cc: io...@lists.linux-foundation.org; linux-ker...@vger.kernel.org;
kvm@vger.kernel.org
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-19:
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
set
Wu, Feng wrote on 2014-12-19:
iommu-boun...@lists.linux-foundation.org wrote on
mailto:iommu-boun...@lists.linux-foundation.org] On Behalf
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-19:
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
set
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-19:
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN'
is set
Wu
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-19:
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
set
Wu, Feng wrote on 2014-12-19:
Zhang, Yang Z wrote on 2014-12-19:
Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN'
is set
Wu
Zhang Haoyu wrote on 2014-12-11:
Then?
It's already in upstream KVM
commit 4114c27d450bef228be9c7b0c40a888e18a3a636
Author: Wei Wang wei.w.w...@intel.com
Date: Wed Nov 5 10:53:43 2014 +0800
KVM: x86: reset RVI upon system reset
A bug was reported as follows: when running Windows
Wu, Feng wrote on 2014-11-13:
kvm-ow...@vger.kernel.org wrote on 2014-11-12:
kvm@vger.kernel.org; io...@lists.linux-foundation.org;
linux-ker...@vger.kernel.org
Subject: Re: [PATCH 05/13] KVM: Update IRTE according to guest
interrupt configuration changes
On 12/11/2014 10:19, Wu,
Wu, Feng wrote on 2014-11-13:
Zhang, Yang Z wrote on 2014-11-13:
kvm@vger.kernel.org; io...@lists.linux-foundation.org;
linux-ker...@vger.kernel.org
Subject: RE: [PATCH 05/13] KVM: Update IRTE according to guest
interrupt configuration changes
Wu, Feng wrote on 2014-11-13:
kvm-ow
Paolo Bonzini wrote on 2014-11-11:
On 11/11/2014 10:20, Wu, Feng wrote:
Since legacy KVM device assignment is effectively deprecated, have
you considered how we might do this with VFIO? Thanks,
I haven't thought about how to enable this in VFIO so far. I think I
can continue to
Paolo Bonzini wrote on 2014-11-05:
On 05/11/2014 10:02, Chen, Tiejun wrote:
I think both are ok.
If we zero max_irr in vmx_set_rvi(), we still need this check:
if ((is_guest_mode(vcpu) nested_exit_on_intr(vcpu)) || max_irr
==
-1)
No, I don't think we need to add this.
You don't,
Jan Kiszka wrote on 2014-10-20:
Hi all,
we just started a test with Jailhouse in a VM on a decently recent Intel
box. It has APICv / posted interrupts support. And it breaks Jailhouse
activation (L1 breakage, host seems to be fine). Loading kvm-intel with
enable_apicv=0 resolves the issue.
Paolo Bonzini wrote on 2014-08-27:
Il 27/08/2014 16:05, Wei Wang ha scritto:
Guest may mask the IOAPIC entry before issue EOI. In such case, EOI
will not be intercepted by the hypervisor, since the corresponding bit
in eoi_exit_bitmap is not set after the masking of IOAPIC entry.
The
Chen, Tiejun wrote on 2014-08-15:
On 2014/8/14 3:16, Wei Wang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Guest may mask the IOAPIC entry before issue EOI. In such case,
EOI will not be intercepted by hypervisor due to the corrensponding
s/corrensponding/corresponding
bit in eoi
Paolo Bonzini wrote on 2014-08-07:
Il 07/08/2014 03:31, Zhang, Yang Z ha scritto:
Let me give an example to see whether my concern is a real problem:
Guest allocates a vector and set it in IOAPIC entry to deliver
interrupt. Later it masks the IOAPIC entry(means stop the
corresponding device
Paolo Bonzini wrote on 2014-08-05:
Il 05/08/2014 09:56, Zhang, Yang Z ha scritto:
Wanpeng Li wrote on 2014-08-04:
This patch fix bug
https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature
Paolo Bonzini wrote on 2014-07-31:
Currently, the EOI exit bitmap (used for APICv) does not include
interrupts that are masked. However, this can cause a bug that manifests
as an interrupt storm inside the guest. Alex Williamson reported the
bug and is the one who really debugged this; I
Paolo Bonzini wrote on 2014-08-06:
Il 06/08/2014 16:03, Zhang, Yang Z ha scritto:
Paolo Bonzini wrote on 2014-07-31:
Probably, the guest is masking the interrupt in the redirection
table in the interrupt routine, i.e. while the interrupt is set in a
LAPIC's ISR.
The simplest fix
Wanpeng Li wrote on 2014-08-04:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for certain VMM.
We map virtual APIC page address and TPR threshold from L1 VMCS. If
Paolo Bonzini wrote on 2014-08-01:
Il 01/08/2014 02:57, Zhang, Yang Z ha scritto:
TPR_THRESHOLD will be likely written as zero, but the processor
will never use it anyway. It's just a small optimization because
nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW) will almost always
be true
Paolo Bonzini wrote on 2014-07-31:
Il 31/07/2014 10:03, Wanpeng Li ha scritto:
One thing:
+ if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
+ vmcs_write32(TPR_THRESHOLD, vmcs12-tpr_threshold);
I think you can just do this write unconditionally, since most
hypervisors will
Hi all,
I see the deadline of CFP for KVM forum is July 27, 2014. But I found there is
no kvm forum selection list when I tried to submit a presentation yesterday. Is
the CFP closed early than expected?
BTW, it is in July 27 in US when sending this mail.
best regards
yang
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To unsubscribe
, slowly. The original idea of
this fix vid injection patch is from Zhang, Yang Z
yang.z.zh...@intel.com.
Interrupt which delivered by vid should be injected to L1 by L0 if
current is in L1, or should be injected to L2 by L0 through the old
injection way if L1 doesn't have set
Paolo Bonzini wrote on 2014-07-17:
Il 17/07/2014 06:56, Wanpeng Li ha scritto:
nested_exit_intr_ack_set(vcpu)) {
int irq = kvm_cpu_get_interrupt(vcpu);
+
+if (irq 0 kvm_apic_vid_enabled(vcpu-kvm))
+irq = kvm_get_apic_interrupt(vcpu);
Wanpeng Li wrote on 2014-07-17:
WARNING: CPU: 9 PID: 7251 at arch/x86/kvm/vmx.c:8719
nested_vmx_vmexit+0xa4/0x233 [kvm_intel]() Modules linked in: tun
nfsv3 nfs_acl auth_rpcgss oid_registry nfsv4 dns_resolver nfs fscache
lockd sunrpc pci_stub netconsole kvm_intel kvm bridge stp llc autofs4
Paolo Bonzini wrote on 2014-03-27:
Il 27/03/2014 13:25, Feng Wu ha scritto:
+void update_permission_bitmask(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu, bool ept)
{
unsigned bit, byte, pfec;
u8 map;
-bool fault, x, w, u, wf, uf, ff, smep;
+bool fault, x, w,
Vadim Rozenfeld wrote on 2014-02-24:
On Mon, 2014-02-24 at 03:01 +, Zhang, Yang Z wrote:
Vadim Rozenfeld wrote on 2014-02-14:
On Fri, 2014-02-14 at 02:35 +, Liu, RongrongX wrote:
Vadim Rozenfeld wrote on 2014-02-12:
On Wed, 2014-02-12 at 01:33 +, Zhang, Yang Z wrote:
Vadim
Vadim Rozenfeld wrote on 2014-02-14:
On Fri, 2014-02-14 at 02:35 +, Liu, RongrongX wrote:
Vadim Rozenfeld wrote on 2014-02-12:
On Wed, 2014-02-12 at 01:33 +, Zhang, Yang Z wrote:
Vadim Rozenfeld wrote on 2014-02-10:
On Mon, 2014-02-10 at 08:21 +, Zhang, Yang Z wrote:
Hi Vadim
Vadim Rozenfeld wrote on 2014-02-10:
On Mon, 2014-02-10 at 08:21 +, Zhang, Yang Z wrote:
Hi Vadim,
Do you know the latest status of Hyper-v Enlightenments supporting in KVM?
Like how many Hyper-v interfaces are supported in KVM?
Hi Yang,
There is no many at the moment. KVM
Hi Vadim,
Do you know the latest status of Hyper-v Enlightenments supporting in KVM? Like
how many Hyper-v interfaces are supported in KVM?
best regards
yang
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More majordomo
Alex Williamson wrote on 2013-12-24:
David,
Any comments on this patch? Thanks,
Hi Alex,
There do have some IOMMUs will treat SNP bit in the PTE as reserved (0) and
will cause a reserved field violation fault if it is set but hardware not
support snoop-control(bit 7 in ECAP_REG is 0).
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2-L0 with some
reasons not emulated by L1, preemption timer value should be save in such
exits.
2. Add support of Save VMX-preemption timer value
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2-L0
with some reasons
Arthur Chunqi Li wrote on 2013-09-05:
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 10:39:59AM +0200, Jan Kiszka wrote:
From: Jan Kiszka jan.kis...@siemens.com
If nested EPT is enabled, the L2 guest may change CR3 without any exits.
We therefore have to read the current value from the VMCS when
switching to L1.
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 11:44:41AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 10:39:59AM +0200, Jan Kiszka wrote:
From: Jan Kiszka jan.kis...@siemens.com
If nested EPT is enabled, the L2 guest may change CR3
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 02:12:51PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 11:44:41AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-08-06:
On Tue, Aug 06, 2013 at 10:39:59AM +0200, Jan Kiszka wrote:
From
Jan Kiszka wrote on 2013-08-02:
On 2013-08-02 05:04, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-08-01:
From: Nadav Har'El n...@il.ibm.com
Recent KVM, since
http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
switch the EFER MSR when EPT is used and the host and guest have
Gleb Natapov wrote on 2013-08-01:
From: Nadav Har'El n...@il.ibm.com
Recent KVM, since
http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
switch the EFER MSR when EPT is used and the host and guest have different
NX bits. So if we add support for nested EPT (L1 guest using EPT to
-Original Message-
From: Gleb Natapov [mailto:g...@redhat.com]
Sent: Monday, July 08, 2013 8:38 PM
To: Zhang, Yang Z
Cc: Jan Kiszka; Paolo Bonzini; Nakajima, Jun; kvm@vger.kernel.org
Subject: Re: [PATCH v3 01/13] nEPT: Support LOAD_IA32_EFER entry/exit
controls for L1
On Thu, Jul
Gleb Natapov wrote on 2013-07-02:
On Tue, Jul 02, 2013 at 05:34:56PM +0200, Jan Kiszka wrote:
On 2013-07-02 17:15, Gleb Natapov wrote:
On Tue, Jul 02, 2013 at 04:28:56PM +0200, Jan Kiszka wrote:
On 2013-07-02 15:59, Gleb Natapov wrote:
On Tue, Jul 02, 2013 at 03:01:24AM +, Zhang, Yang Z
Il 03/07/2013 10:24, Arthur Chunqi Li ha scritto:
Hi Gleb and Paolo,
When I write test cases for nested virt and found that reading/writing
IA32_FEATURE_CONTROL will be simply ignored or return 0 (in
arch/x86/kvm/vmx.c) in VM. Checking this MSR will be done by some
hypervisors (e.g. NOVA)
Since this series is pending in mail list for long time. And it's really a big
feature for Nested. Also, I doubt the original authors(Jun and Nahav)should not
have enough time to continue it. So I will pick it up. :)
See comments below:
Paolo Bonzini wrote on 2013-05-20:
Il 19/05/2013 06:52,
Yangminqiang wrote on 2013-05-03:
Nakajima, Jun wrote on 2013-04-26:
Subject: Re: [PATCH v10 7/7] KVM: VMX: Use posted interrupt to deliver
virtual
interrupt
On Fri, Apr 26, 2013 at 2:29 AM, Yangminqiang yangminqi...@huawei.com
wrote:
Ivytown or newer platform supported it.
Ivytown?
Yangminqiang wrote on 2013-04-26:
Hi Yang Zhang,
Could you please let me know your CPU model or the CPU models which
supports apic-v which your patch requires()? So that I could try you
patches.
Intel Software Developer's Manualm, Volume 3C,
System Programming Guide, Part 3. Ch29,
David Rientjes wrote on 2013-04-18:
On Wed, 17 Apr 2013, Randy Dunlap wrote:
On 04/17/13 16:12, David Rientjes wrote:
The build fails when CONFIG_SMP is disabled:
arch/x86/kvm/vmx.c: In function 'vmx_deliver_posted_interrupt':
arch/x86/kvm/vmx.c:3950:3: error: 'apic' undeclared
Randy Dunlap wrote on 2013-04-18:
On 04/17/13 17:35, Zhang, Yang Z wrote:
David Rientjes wrote on 2013-04-18:
On Wed, 17 Apr 2013, Randy Dunlap wrote:
On 04/17/13 16:12, David Rientjes wrote:
The build fails when CONFIG_SMP is disabled:
arch/x86/kvm/vmx.c: In function
Gleb Natapov wrote on 2013-04-11:
On Thu, Apr 11, 2013 at 01:03:30AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-10:
On Wed, Apr 10, 2013 at 09:22:50PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
The follwoing patches are adding the Posted Interrupt
Gleb Natapov wrote on 2013-04-11:
On Wed, Apr 10, 2013 at 09:22:20PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Current interrupt coalescing logci which only used by RTC has conflict
with Posted Interrupt.
This patch introduces a new mechinism to use eoi to track
Gleb Natapov wrote on 2013-04-11:
On Thu, Apr 11, 2013 at 07:54:01AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-11:
On Wed, Apr 10, 2013 at 09:22:20PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Current interrupt coalescing logci which only used by RTC
Gleb Natapov wrote on 2013-04-10:
On Wed, Apr 10, 2013 at 09:22:57PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
If posted interrupt is avaliable, then uses it to inject virtual
interrupt to guest.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
Gleb Natapov wrote on 2013-04-10:
On Wed, Apr 10, 2013 at 09:22:50PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
The follwoing patches are adding the Posted Interrupt supporting to KVM:
The first patch enables the feature 'acknowledge interrupt on vmexit'.Since
it is
Gleb Natapov wrote on 2013-04-09:
On Mon, Apr 08, 2013 at 10:17:46PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
arch/x86/kvm/lapic.c |9 +++ arch/x86/kvm/lapic.h |2 +
virt/kvm/ioapic.c| 60
Gleb Natapov wrote on 2013-04-09:
On Mon, Apr 08, 2013 at 10:23:22PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
If posted interrupt is avaliable, then uses it to inject virtual
interrupt to guest.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
Paolo Bonzini wrote on 2013-04-10:
Il 08/04/2013 16:23, Yang Zhang ha scritto:
+ * interrupt from PIR in next vmentry.
+ */
+static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
+{
+struct vcpu_vmx *vmx = to_vmx(vcpu);
+int r;
+
+if
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 01:16:51PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 01:05:02PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 12:39:32PM +, Zhang, Yang Z wrote
Gleb Natapov wrote on 2013-04-08:
On Mon, Apr 08, 2013 at 11:21:34AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 01:16:51PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 01:05:02PM +, Zhang, Yang Z wrote
Gleb Natapov wrote on 2013-04-07:
On Sun, Apr 07, 2013 at 02:30:15AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2013-04-04:
On Mon, Apr 01, 2013 at 08:40:13AM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
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