On 07.01.2009, at 12:16, Andre Przywara wrote:
Alexander Graf wrote:
Well if I could take the FlexMigration design into account when
putting
variables in the vcpu context, that'd be great. But I can't seem to
find
it in the Intel documentation, so I'll leave it for now.
Not real documentat
Alexander Graf wrote:
Well if I could take the FlexMigration design into account when putting
variables in the vcpu context, that'd be great. But I can't seem to find
it in the Intel documentation, so I'll leave it for now.
Not real documentation (tell me if you find some!), but this code shows
Avi Kivity wrote:
> Alexander Graf wrote:
>>> Note that Intel has similar functionality, called FlexMigration
>>> IIRC, likely using different MSRs.
>>
>> Hum. I'll take a look at it to see if that's as easy to implement then.
>
> It's probably easy (well supporting both might be tricky) but if you
Alexander Graf wrote:
Note that Intel has similar functionality, called FlexMigration IIRC,
likely using different MSRs.
Hum. I'll take a look at it to see if that's as easy to implement then.
It's probably easy (well supporting both might be tricky) but if you
don't have a real test case th
On 07.01.2009, at 11:07, Avi Kivity wrote:
Alexander Graf wrote:
Current AMD CPUs support masking of CPUID bits. Using this
functionality,
a VMM can limit what features are exposed to the guest, even if
it's not
using SVM/VMX.
While I'm not aware of any open source hypervisor that uses th
Alexander Graf wrote:
Current AMD CPUs support masking of CPUID bits. Using this functionality,
a VMM can limit what features are exposed to the guest, even if it's not
using SVM/VMX.
While I'm not aware of any open source hypervisor that uses these MSRs
atm, VMware ESX does and patches exist fo
Current AMD CPUs support masking of CPUID bits. Using this functionality,
a VMM can limit what features are exposed to the guest, even if it's not
using SVM/VMX.
While I'm not aware of any open source hypervisor that uses these MSRs
atm, VMware ESX does and patches exist for Xen, where trapping CP