GCC doesn't warn that ((u32)e-index 24) == 0x800 is always false?
I think SDM says '(e-index 8) == 0x8'.
Missed that. Thank you.
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Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of it.
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Will send fixed patch this evening.
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Hi all,
On Wed, Dec 10, 2014 at 08:07:45AM -0100, Eugene Korenevsky wrote:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of
On Wed, Dec 10, 2014 at 08:13:58AM -0100, Eugene Korenevsky wrote:
Will send fixed patch this evening.
Please see my reply to another thread.
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2014-12-10 17:01 GMT+08:00 Wanpeng Li wanpeng...@linux.intel.com:
Hi all,
On Wed, Dec 10, 2014 at 08:07:45AM -0100, Eugene Korenevsky wrote:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a
Eugene Korenevsky ekorenev...@gmail.com writes:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of it.
I was suggesting
Eugene Korenevsky ekorenev...@gmail.com writes:
Several hypervisors use MSR loading/storing to run guests.
This patch implements emulation of this feature and allows these
hypervisors to work in L1.
The following is emulated:
- Loading MSRs on VM-entries
- Saving MSRs on VM-exits
-
I have added Jan and Wincy to the CC list since they reviewed your earlier
proposal.
I think it would be better to split this up as I mentioned earlier, however,
if the other reviewers and the maintainer don't have objections, I am ok :)
OK, the final patch is following.
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Eugene
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To
Several hypervisors use MSR loading/storing to run guests on VMX.
This patch implements emulation of this feature and allows these
hypervisors to work in L1.
The following is emulated:
- Loading MSRs on VM-entries
- Saving MSRs on VM-exits
- Loading MSRs on VM-exits
Actions taken on loading
2014-12-10 00:18+0300, Eugene Korenevsky:
+static bool vmx_load_msr_entry_verify(struct kvm_vcpu *vcpu,
+ struct vmx_msr_entry *e)
[...]
+ /* x2APIC MSR accesses are not allowed */
+ if (apic_x2apic_mode(vcpu-arch.apic) (e-index 24) == 0x800)
+
2014-12-10 5:12 GMT+08:00 Eugene Korenevsky ekorenev...@gmail.com:
I have added Jan and Wincy to the CC list since they reviewed your earlier
proposal.
I think it would be better to split this up as I mentioned earlier, however,
if the other reviewers and the maintainer don't have objections,
Several hypervisors use MSR loading/storing to run guests.
This patch implements emulation of this feature and allows these
hypervisors to work in L1.
The following is emulated:
- Loading MSRs on VM-entries
- Saving MSRs on VM-exits
- Loading MSRs on VM-exits
Actions taken on loading MSRs:
- MSR
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