On 17.02.2012, at 22:12, Scott Wood wrote:
On 02/17/2012 11:13 AM, Alexander Graf wrote:
From: Scott Wood scottw...@freescale.com
Chips such as e500mc that implement category E.HV in Power ISA 2.06
provide hardware virtualization features, including a new MSR mode for
guest state. The
From: Scott Wood scottw...@freescale.com
Chips such as e500mc that implement category E.HV in Power ISA 2.06
provide hardware virtualization features, including a new MSR mode for
guest state. The guest OS can perform many operations without trapping
into the hypervisor, including transitions to
On 02/17/2012 11:13 AM, Alexander Graf wrote:
From: Scott Wood scottw...@freescale.com
Chips such as e500mc that implement category E.HV in Power ISA 2.06
provide hardware virtualization features, including a new MSR mode for
guest state. The guest OS can perform many operations without
On 02/17/2012 11:13 AM, Alexander Graf wrote:
From: Scott Wood scottw...@freescale.com
Chips such as e500mc that implement category E.HV in Power ISA 2.06
provide hardware virtualization features, including a new MSR mode for
guest state. The guest OS can perform many operations without