On Fri, Nov 30, 2012 at 09:40:37PM +, Christoffer Dall wrote:
On Mon, Nov 19, 2012 at 10:07 AM, Will Deacon will.dea...@arm.com wrote:
Why are PIPT caches affected by this? The virtual address is irrelevant.
The comment is slightly misleading, and I'll update it. Just so we're
On Mon, Dec 3, 2012 at 8:06 AM, Will Deacon will.dea...@arm.com wrote:
On Fri, Nov 30, 2012 at 09:40:37PM +, Christoffer Dall wrote:
On Mon, Nov 19, 2012 at 10:07 AM, Will Deacon will.dea...@arm.com wrote:
Why are PIPT caches affected by this? The virtual address is irrelevant.
The
On Mon, Nov 19, 2012 at 10:07 AM, Will Deacon will.dea...@arm.com wrote:
On Sat, Nov 10, 2012 at 03:43:42PM +, Christoffer Dall wrote:
Handles the guest faults in KVM by mapping in corresponding user pages
in the 2nd stage page tables.
We invalidate the instruction cache by MVA whenever
On Sat, Nov 10, 2012 at 03:43:42PM +, Christoffer Dall wrote:
Handles the guest faults in KVM by mapping in corresponding user pages
in the 2nd stage page tables.
We invalidate the instruction cache by MVA whenever we map a page to the
guest (no, we cannot only do it when we have an iabt
Handles the guest faults in KVM by mapping in corresponding user pages
in the 2nd stage page tables.
We invalidate the instruction cache by MVA whenever we map a page to the
guest (no, we cannot only do it when we have an iabt because the guest
may happily read/write a page before hitting the
