On 02/21/2011 07:28 PM, Roedel, Joerg wrote:
- what's the cost of wrmsr(TSC_MULT)?
Hard to tell by now because I only have numbers for pre-production
hardware.
Can you ask your hardware people what the cost will likely be? msrs are
often expensive, and here we have two in the lightweight
On Tue, Feb 22, 2011 at 05:11:42AM -0500, Avi Kivity wrote:
On 02/21/2011 07:28 PM, Roedel, Joerg wrote:
- what's the cost of wrmsr(TSC_MULT)?
Hard to tell by now because I only have numbers for pre-production
hardware.
Can you ask your hardware people what the cost will likely be?
On 02/22/2011 12:35 PM, Roedel, Joerg wrote:
This doesn't really work, since we don't know on what host the TSC
calibration loop ran:
- start guest on host H1
- migrate it around, now it's on host H2
- guest reboots, reruns calibration loop
- migrate it around some more, now it's on
On Tue, Feb 22, 2011 at 05:41:53AM -0500, Avi Kivity wrote:
On 02/22/2011 12:35 PM, Roedel, Joerg wrote:
This doesn't really work, since we don't know on what host the TSC
calibration loop ran:
- start guest on host H1
- migrate it around, now it's on host H2
- guest
On 02/22/2011 01:11 PM, Roedel, Joerg wrote:
Ok, so your scenario is
- boot on host H1
- no intervening migrations
- migrate to host Hnew
- all succeeding migrations are only to new hosts or back to H1
This is somewhat artificial, and not very different from an all-new cluster.
On Sun, Feb 13, 2011 at 10:19:19AM -0500, Avi Kivity wrote:
On 02/09/2011 07:29 PM, Joerg Roedel wrote:
Hi Avi, Marcelo,
here is the patch-set to implement the TSC-scaling feature of upcoming
AMD CPUs. When this feature is supported the CPU provides a new MSR
which holds a multiplier
On 02/21/2011 12:28 PM, Roedel, Joerg wrote:
On Sun, Feb 13, 2011 at 10:19:19AM -0500, Avi Kivity wrote:
On 02/09/2011 07:29 PM, Joerg Roedel wrote:
Hi Avi, Marcelo,
here is the patch-set to implement the TSC-scaling feature of upcoming
AMD CPUs. When this feature is supported the
On 02/09/2011 07:29 PM, Joerg Roedel wrote:
Hi Avi, Marcelo,
here is the patch-set to implement the TSC-scaling feature of upcoming
AMD CPUs. When this feature is supported the CPU provides a new MSR
which holds a multiplier for the hardware TSC which is applied on the
value rdtsc[p] and reads
