It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it cannot set IA32_DEBUGCTL for itself (see
kvm_set_msr_common).
Am I missing something?
Regards,
Nadav
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To unsubscribe from this
On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter Maydell wrote:
On 28 April 2015 at 09:42, Alex Bennée alex.ben...@linaro.org wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Does the kernel already have a conveniently implemented inject
exception into guest lump of code? If so it might
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter Maydell wrote:
On 28 April 2015 at 09:42, Alex Bennée alex.ben...@linaro.org wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Does the kernel already have a conveniently implemented
All calls to context_tracking_enter and context_tracking_exit
are already checking context_tracking_is_enabled, except the
context_tracking_user_enter and context_tracking_user_exit
functions left in for the benefit of assembly calls.
Pull the check up to those functions, by making them simple
On 28/04/2015 12:32, Christian Borntraeger wrote:
Some architectures already have irq disabled when calling
kvm_guest_exit. Push down the disabling into the architectures
to avoid double disabling. This also allows to replace
irq_save with irq_disable which might be cheaper.
arm and mips
On 28/04/2015 16:10, Christian Borntraeger wrote:
Alternatively, the irq-disabled versions could be called
__kvm_guest_{enter,exit}. Then you can use those directly when it makes
sense.
..having a special __kvm_guest_{enter,exit} without the WARN_ON might be even
the cheapest way. In
On 28/04/2015 16:00, Radim Krčmář wrote:
kvm_ioapic_eoi_inject_work() can be called after ioapic has been freed,
fix it by cancelling its delayed work via a slightly better freeing.
(Could have been a one-liner.)
Signed-off-by: Radim Krčmář rkrc...@redhat.com
---
I noticed it while
Am 28.04.2015 um 13:37 schrieb Paolo Bonzini:
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -891,7 +891,9 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct
kvm_vcpu *vcpu,
/* We get here with MSR.EE=1 */
+local_irq_disable();
kvm_ioapic_eoi_inject_work() can be called after ioapic has been freed,
fix it by cancelling its delayed work via a slightly better freeing.
(Could have been a one-liner.)
Signed-off-by: Radim Krčmář rkrc...@redhat.com
---
I noticed it while reviewing the KVM: x86: drop unneeded null test,
so
This extends the sanity checks done on known common Qemu binary
paths when the user supplies a QEMU= on the command line
Fixes: b895b967db94937d5b593c51b95eb32d2889a764
Signed-off-by: Bandan Das b...@redhat.com
---
x86/run | 43 +++
1 file changed, 19
On 04/28/2015 07:36 AM, Paolo Bonzini wrote:
All calls to context_tracking_enter and context_tracking_exit
are already checking context_tracking_is_enabled, except the
context_tracking_user_enter and context_tracking_user_exit
functions left in for the benefit of assembly calls.
Pull the
Jan Kiszka jan.kis...@siemens.com wrote:
Am 2015-04-28 um 13:43 schrieb Paolo Bonzini:
On 28/04/2015 13:42, Nadav Amit wrote:
It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it
On 28/04/2015 14:00, Jan Kiszka wrote:
It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for
the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it cannot set IA32_DEBUGCTL for itself (see
kvm_set_msr_common).
Am I
Juan Quintela quint...@redhat.com wrote:
Hi
Please, send any topic that you are interested in covering.
As there are no topics for Today call, call got cancelled.
Thanks, Juan.
Call details:
By popular demand, a google calendar public entry with it
On 28/04/2015 13:42, Nadav Amit wrote:
It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it cannot set IA32_DEBUGCTL for itself (see
kvm_set_msr_common).
Am I missing
On 04/28/2015 07:36 AM, Paolo Bonzini wrote:
All calls to context_tracking_enter and context_tracking_exit
are already checking context_tracking_is_enabled, except the
context_tracking_user_enter and context_tracking_user_exit
functions left in for the benefit of assembly calls.
Pull the
Am 2015-04-28 um 13:43 schrieb Paolo Bonzini:
On 28/04/2015 13:42, Nadav Amit wrote:
It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it cannot set IA32_DEBUGCTL for itself
On Thu, Apr 23, 2015 at 05:12:42PM -0400, Luiz Capitulino wrote:
If you try to enable NOHZ_FULL on a guest today, you'll get
the following error when the guest tries to deactivate the
scheduler tick:
WARNING: CPU: 3 PID: 2182 at kernel/time/tick-sched.c:192
can_stop_full_tick+0xb9/0x290()
On Fri, Apr 24, 2015 at 10:36:14PM -0300, Marcelo Tosatti wrote:
Drop unnecessary rdtsc_barrier(), as has been determined empirically,
see 057e6a8c660e95c3f4e7162e00e2fee1fc90c50d for details.
Noticed by Andy Lutomirski.
Improves clock_gettime() by approximately 15% on
Intel i7-3520M @
This fixes a regression introduced in commit 25fedfca94cf, KVM: PPC:
Book3S HV: Move vcore preemption point up into kvmppc_run_vcpu, which
leads to a user-triggerable oops.
In the case where we try to run a vcore on a physical core that is
not in single-threaded mode, or the vcore has too many
Hi,
Sorry to bother you all.
In ESXI 6.0 you can have 4096 interrupt vectors if you have 32 CPU's,
so 128 interrupt vectors per CPU.
How does KVM handle this (I haven't bought the server hardware yet)?
Basically I want to have 64 guests on a x86 KVM host, all of which
will need 4 x SR-IOV
From: Paolo Bonzini
Sent: Tuesday, April 21, 2015 10:48 AM
Hi, big thanks to all involved in this and to Brad for endless reboots ;-)
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
Fixes: 33e4c68656a2e461b296ce714ec322978de85412
Cc: sta...@vger.kernel.org # 2.6.32+
Signed-off-by:
Peter Maydell peter.mayd...@linaro.org writes:
On 27 April 2015 at 21:04, Christoffer Dall christoffer.d...@linaro.org
wrote:
On Thu, Apr 23, 2015 at 03:26:53PM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Mar 31, 2015 at 04:08:04PM +0100, Alex
If the null test is needed, the call to cancel_delayed_work_sync would have
already crashed. Normally, the destroy function should only be called
if the init functoin has succeeded, in which case ioapic is not null.
Does your commit message need a small fix?
Regards,
Markus
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To unsubscribe
I was able to get rid of some nanoseconds for a guest exit loop
on s390. I did my best to not break other architectures but
review and comments on the general approach is welcome.
Downside is that the existing irq_save things will just work
no matter what the callers have done, the new code must
Some architectures already have irq disabled when calling
kvm_guest_exit. Push down the disabling into the architectures
to avoid double disabling. This also allows to replace
irq_save with irq_disable which might be cheaper.
arm and mips already have interrupts disabled. s390/power/x86
need
local_irq_disable can be cheaper than local_irq_save, especially
when done only once instead of twice. We can push down the
local_irq_save (and replace it with local_irq_disable) to
save some cycles.
x86, mips and arm already disable the interrupts before calling
kvm_guest_enter. Here we save one
On 28 April 2015 at 09:42, Alex Bennée alex.ben...@linaro.org wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Does the kernel already have a conveniently implemented inject
exception into guest lump of code? If so it might be less effort
to do it that way round, maybe.
So you pointed
When REP-string instruction is preceded with an address-size prefix,
ECX/EDI/ESI are used as the operation counter and pointers. When they are
updated, the high 32-bits of RCX/RDI/RSI are cleared, similarly to the way they
are updated on every 32-bit register operation. Fix it.
Signed-off-by:
This patch-set fixes KVM behavior when handling a REP-string instruction that
runs with an address-size of 32-bit. In this case ECX/EDI/ESI are used as
counter and pointers, and the high 32-bits should be cleared.
The first patch handles with the simple case. The second one handles the
When a REP-string is executed in 64-bit mode with an address-size prefix,
ECX/EDI/ESI are used as counter and pointers. When ECX is initially zero, Intel
CPUs clear the high 32-bits of RCX, and recent Intel CPUs update the high bits
of the pointers in MOVS/STOS. This behavior is specific to Intel
On Tue, Apr 28, 2015 at 10:36:52AM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras pau...@samba.org writes:
The reference (R) and change (C) bits in a HPT entry can be set by
hardware at any time up until the HPTE is invalidated and the TLB
invalidation sequence has completed. This means
On 27/04/2015 22:35, Julia Lawall wrote:
From: Julia Lawall julia.law...@lip6.fr
If the null test is needed, the call to cancel_delayed_work_sync would have
already crashed. Normally, the destroy function should only be called
if the init functoin has succeeded, in which case ioapic is
If get_free_page() fails for nested bitmap area, it's evident that
we are gonna get screwed anyway but returning failure because we failed
allocating memory for a nested structure seems like an unnecessary big
hammer. Also, save the call for later; after we are done with other
non-nested
On 28/04/2015 16:10, Christian Borntraeger wrote:
Alternatively, the irq-disabled versions could be called
__kvm_guest_{enter,exit}. Then you can use those directly when it makes
sense.
..having a special __kvm_guest_{enter,exit} without the WARN_ON might be even
the cheapest way. In
Am 28.04.2015 um 13:37 schrieb Paolo Bonzini:
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -891,7 +891,9 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct
kvm_vcpu *vcpu,
/* We get here with MSR.EE=1 */
+local_irq_disable();
On 28/04/2015 12:32, Christian Borntraeger wrote:
Some architectures already have irq disabled when calling
kvm_guest_exit. Push down the disabling into the architectures
to avoid double disabling. This also allows to replace
irq_save with irq_disable which might be cheaper.
arm and mips
This fixes a regression introduced in commit 25fedfca94cf, KVM: PPC:
Book3S HV: Move vcore preemption point up into kvmppc_run_vcpu, which
leads to a user-triggerable oops.
In the case where we try to run a vcore on a physical core that is
not in single-threaded mode, or the vcore has too many
I was able to get rid of some nanoseconds for a guest exit loop
on s390. I did my best to not break other architectures but
review and comments on the general approach is welcome.
Downside is that the existing irq_save things will just work
no matter what the callers have done, the new code must
Some architectures already have irq disabled when calling
kvm_guest_exit. Push down the disabling into the architectures
to avoid double disabling. This also allows to replace
irq_save with irq_disable which might be cheaper.
arm and mips already have interrupts disabled. s390/power/x86
need
local_irq_disable can be cheaper than local_irq_save, especially
when done only once instead of twice. We can push down the
local_irq_save (and replace it with local_irq_disable) to
save some cycles.
x86, mips and arm already disable the interrupts before calling
kvm_guest_enter. Here we save one
On Tue, Apr 28, 2015 at 10:36:52AM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras pau...@samba.org writes:
The reference (R) and change (C) bits in a HPT entry can be set by
hardware at any time up until the HPTE is invalidated and the TLB
invalidation sequence has completed. This means
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