Hi Zhang,
No I haven't seen such problem
Which kernel version are you running?
Host kernel: RHEL7-RC1(linux-3.10.0).
Does it include the latest lazy eli changes?
lazy eli or lazy eoi?
How to confirm whether lazy eli has been included?
Btw, hv_spinlocks=0xfff is a pretty huge value.
which
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always clear DBSR.
Now if userspace has to always clear
This patch adds rfdi instruction emulation which is required for
guest debug hander on BOOKE-HV
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/booke_emulate.c| 13 +
2 files changed, 14 insertions(+)
This patch changes the default behavior of MSRP_DEP, that is
guest is not allowed to change the MSR_DE, to guest can change
MSR_DE. When userspace is debugging guest then it override the
default behavior and set MSRP_DEP. This stops guest to change
MSR_DE when userspace is debugging guest.
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt
This patch changes the default behavior of MSRP_DEP, that is
guest is not allowed to change the MSR_DE, to guest can change
MSR_DE. When userspace is debugging guest then it override the
default behavior and set MSRP_DEP. This stops guest to change
MSR_DE when userspace is debugging guest.
This patchset adds debug register and interrupt emulation support
for guest, which enables running gdb/kgdb etc in guest.
Bharat Bhushan (5):
KVM: PPC: BOOKE: allow debug interrupt at debug level
KVM: PPC: BOOKE : Emulate rfdi instruction
KVM: PPC: BOOKE: Allow guest to change MSR_DE
KVM:
This patch adds rfdi instruction emulation which is required for
guest debug hander on BOOKE-HV
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
-msr update based on guest_debug done under _set_msr(); so removed same check
here
arch/powerpc/include/asm/kvm_host.h | 1 +
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always clear DBSR.
Now if userspace has to always clear
Hi
Please, send any topic that you are interested in covering.
Thanks, Juan.
Call details:
15:00 CEST
13:00 UTC
09:00 EDT
Every two weeks
By popular demand, a google calendar public entry with it
Hi Paolo and Gleb,
The following changes since commit 9f6226a762c7ae02f6a23a3d4fc552dafa57ea23:
arch: x86: kvm: x86.c: Cleaning up variable is set more than once (2014-06-30
16:52:04 +0200)
are available in the git repository at:
From: Marc Zyngier marc.zyng...@arm.com
Move the GICH_EISR access to its own function.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/kvm/arm_vgic.h | 1 +
From: Marc Zyngier marc.zyng...@arm.com
Move the GICH_ELRSR access to its own functions, and add them to
the vgic_ops structure.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
From: Marc Zyngier marc.zyng...@arm.com
In order to make way for the GICv3 registers, move the v2-specific
registers to their own structure.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier
From: Marc Zyngier marc.zyng...@arm.com
A few GICv2 low-level function are actually very useful to GICv3,
and it makes some sense to share them across the two drivers.
They end-up in their own file, with an additional parameter used
to ensure an optional synchronization (unused on GICv2).
Cc:
From: Marc Zyngier marc.zyng...@arm.com
The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
-
From: Kim Phillips kim.phill...@linaro.org
A userspace process can map device MMIO memory via VFIO or /dev/mem,
e.g., for platform device passthrough support in QEMU.
During early development, we found the PAGE_S2 memory type being used
for MMIO mappings. This patch corrects that by using the
unmap_range() was utterly broken, to quote Marc, and broke in all sorts
of situations. It was also quite complicated to follow and didn't
follow the usual scheme of having a separate iterating function for each
level of page tables.
Address this by refactoring the code and introduce a
From: Marc Zyngier marc.zyng...@arm.com
Instead of directly dealing with the GICH_MISR bits, move the code to
its own function and use a couple of public flags to represent the
actual state.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall
From: Marc Zyngier marc.zyng...@arm.com
In order to split the various register manipulation from the main vgic
code, introduce a vgic_ops structure, and start by abstracting the
LR manipulation code with a couple of accessors.
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
From: Alex Bennée alex.ben...@linaro.org
For correct guest suspend/resume behaviour we need to ensure we include
the generic timer registers for 64 bit guests. As CONFIG_KVM_ARM_TIMER is
always set for arm64 we don't need to worry about null implementations.
However I have re-jigged the
From: Marc Zyngier marc.zyng...@arm.com
Linux has some requirements that must be satisfied in order to boot
on a system built with a GICv3.
Acked-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/arm64/booting.txt | 8
1
From: Alex Bennée alex.ben...@linaro.org
I suspect this is a -ECUTPASTE fault from the initial implementation. If
we don't declare the register ID to be KVM_REG_ARM64 the KVM_GET_ONE_REG
implementation kvm_arm_get_reg() returns -EINVAL and hilarity ensues.
The kvm/api.txt document describes all
From: Victor Kamensky victor.kamen...@linaro.org
Previous patches addresses ARMV7 big-endian virtualiztion,
kvm related issues, so enable ARM_VIRT_EXT for big-endian
now.
Signed-off-by: Victor Kamensky victor.kamen...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
From: Marc Zyngier marc.zyng...@arm.com
Move the code dealing with LR underflow handling to its own functions,
and make them accessible through vgic_ops.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier
From: Marc Zyngier marc.zyng...@arm.com
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by:
From: Marc Zyngier marc.zyng...@arm.com
So far, irqchip_in_kernel() was implemented by testing the value of
vctrl_base, which worked fine with GICv2.
With GICv3, this field is useless, as we're using system registers
instead of a emmory mapped interface. To solve this, add a boolean
flag
From: Marc Zyngier marc.zyng...@arm.com
Just like GICv2 was fixed in 63afbe7a0ac1
(kvm: arm64: vgic: fix hyp panic with 64k pages on juno platform),
mandate the GICV region to be both aligned on a page boundary and
its size to be a multiple of page size.
This prevents a guest from being able to
From: Victor Kamensky victor.kamen...@linaro.org
esr_el2 field of struct kvm_vcpu_fault_info has u32 type.
It should be stored as word. Current code works in LE case
because existing puts least significant word of x1 into
esr_el2, and it puts most significant work of x1 into next
field, which
From: Marc Zyngier marc.zyng...@arm.com
Move the code dealing with enabling the VGIC on to vgic_ops.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/kvm/arm_vgic.h | 1 +
From: Marc Zyngier marc.zyng...@arm.com
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by:
From: Li Liu john.li...@huawei.com
HSCTLR.EE is defined as bit[25] referring to arm manual
DDI0606C.b(p1590).
Reviewed-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Li Liu john.li...@huawei.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/kernel/hyp-stub.S | 4 +---
1
From: Marc Zyngier marc.zyng...@arm.com
An interesting feature of the CP14 encoding is that there is
an overlap between 32 and 64bit registers, meaning they cannot
live in the same table as we did for CP15.
Create separate tables for 64bit CP14 and CP15 registers, and
let the top level handler
From: Victor Kamensky victor.kamen...@linaro.org
Fix issue with 32bit guests running on top of BE KVM host.
Indexes of high and low words of 64bit cp15 register are
swapped in case of big endian code, since 64bit cp15 state is
restored or saved with double word write or read instruction.
Define
From: Marc Zyngier marc.zyng...@arm.com
We already have __hyp_text_{start,end} to express the boundaries
of the HYP text section, and __kvm_hyp_code_{start,end} are getting
in the way of a more modular world switch code.
Just turn __kvm_hyp_code_{start,end} into #defines mapping the
From: Victor Kamensky victor.kamen...@linaro.org
In some cases the mcrr and mrrc instructions in combination with the ldrd
and strd instructions need to deal with 64bit value in memory. The ldrd
and strd instructions already handle endianness within word (register)
boundaries but to get effect of
From: Marc Zyngier marc.zyng...@arm.com
Enable trapping of the debug registers, preventing the guests to
mess with the host state (and allowing guests to use the debug
infrastructure as well).
Reviewed-by: Anup Patel anup.pa...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
From: Victor Kamensky victor.kamen...@linaro.org
Fix vgic_bitmap_get_reg function to return 'right' word address of
'unsigned long' bitmap value in case of BE 64bit image.
Signed-off-by: Victor Kamensky victor.kamen...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
From: Marc Zyngier marc.zyng...@arm.com
Introduce the GICv3 world switch code used to save/restore the
GICv3 context.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
From: Marc Zyngier marc.zyng...@arm.com
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the occurences used by KVM as the code wasn't
merged yet.
Just fix the accessors.
Cc: Will Deacon
From: Victor Kamensky victor.kamen...@linaro.org
Since size of all sys registers is always 8 bytes. Current
code is actually endian agnostic. Just clean it up a bit.
Removed comment about little endian. Change type of pointer
from 'void *' to 'u64 *' to enforce stronger type checking.
From: Marc Zyngier marc.zyng...@arm.com
Commit f0a3eaff71b8 (ARM64: KVM: fix big endian issue in
access_vm_reg for 32bit guest) changed the way we handle CP15
VM accesses, so that all 64bit accesses are done via vcpu_sys_reg.
This looks like a good idea as it solves indianness issues in an
From: Marc Zyngier marc.zyng...@arm.com
Move the GICv2 world switch code into its own file, and add the
necessary indirection to the arm64 switch code.
Also introduce a new type field to the vgic_params structure.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall
From: Marc Zyngier marc.zyng...@arm.com
GICv3 requires the IMO and FMO bits to be tightly coupled with some
of the interrupt controller's register switch.
In order to have similar code paths, move the manipulation of these
bits to the GICv2 switch code.
Acked-by: Catalin Marinas
From: Victor Kamensky victor.kamen...@linaro.org
The vgic h/w registers are little endian; when BE asm code
reads/writes from/to them, it needs to do byteswap after/before.
Byteswap code uses ARM_BE8 wrapper to add swap only if
CONFIG_CPU_BIG_ENDIAN is configured.
Signed-off-by: Victor Kamensky
From: Marc Zyngier marc.zyng...@arm.com
In order to be able to use the DBG_MDSCR_* macros from the KVM code,
move the relevant definitions to the obvious include file.
Also move the debug_el enum to a portion of the file that is guarded
by #ifndef __ASSEMBLY__ in order to use that file from
From: Marc Zyngier marc.zyng...@arm.com
Instead of directly messing with with the GICH_VMCR bits for the CPU
interface save/restore code, add accessors that encode/decode the
entire set of registers exposed by VMCR.
Not the most efficient thing, but given that this code is only used
by the
From: Marc Zyngier marc.zyng...@arm.com
Add handlers for all the AArch64 debug registers that are accessible
from EL0 or EL1. The trapping code keeps track of the state of the
debug registers, allowing for the switch code to implement a lazy
switching strategy.
Reviewed-by: Anup Patel
From: Marc Zyngier marc.zyng...@arm.com
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Reviewed-by: Anup Patel
From: Marc Zyngier marc.zyng...@arm.com
Brutally hack the innocent vgic code, and move the GICv2 specific code
to its own file, using vgic_ops and vgic_params as a way to pass
information between the two blocks.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall
From: Marc Zyngier marc.zyng...@arm.com
Move all the data specific to a given GIC implementation into its own
little structure.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
From: Victor Kamensky victor.kamen...@linaro.org
The __kvm_vcpu_run function returns a 64-bit result in two registers,
which has to be adjusted for BE case.
Signed-off-by: Victor Kamensky victor.kamen...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier
From: Marc Zyngier marc.zyng...@arm.com
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A57 has 6 breakpoints and 4 watchpoints, which gives us a total
of 22 registers only).
Also, we only save/restore them when
From: Victor Kamensky victor.kamen...@linaro.org
Fix code that handles KVM_SET_ONE_REG, KVM_GET_ONE_REG ioctls to work in BE
image. Before this fix get/set_one_reg functions worked correctly only in
LE case - reg_from_user was taking 'void *' kernel address that actually could
be target/source
From: Marc Zyngier marc.zyng...@arm.com
Add the last missing bits that enable GICv2 emulation on top of
GICv3 hardware.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/kvm_host.h | 7 +++
arch/arm64/kvm/Makefile | 2 ++
virt/kvm/arm/vgic.c
From: Victor Kamensky victor.kamen...@linaro.org
In case of guest CPU running in LE mode and host runs in
BE mode we need byteswap data, so read/write is emulated correctly.
Signed-off-by: Victor Kamensky victor.kamen...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
From: Victor Kamensky victor.kamen...@linaro.org
According to recent clarifications of mmio.data array meaning -
the mmio.data array should hold bytes as they would appear in
memory. Vgic is little endian device. And in case of BE image
kernel side that emulates vgic, holds data in BE form. So we
From: Eric Auger eric.au...@linaro.org
Currently when a KVM region is deleted or moved after
KVM_SET_USER_MEMORY_REGION ioctl, the corresponding
intermediate physical memory is not unmapped.
This patch corrects this and unmaps the region's IPA range
in kvm_arch_commit_memory_region using
From: Victor Kamensky victor.kamen...@linaro.org
In case of status register E bit is not set (LE mode) and host runs in
BE mode we need byteswap data, so read/write is emulated correctly.
Signed-off-by: Victor Kamensky victor.kamen...@linaro.org
Reviewed-by: Christoffer Dall
From: Marc Zyngier marc.zyng...@arm.com
Add the necessary documentation to support GICv3.
Cc: Thomas Gleixner t...@linutronix.de
Cc: Mark Rutland mark.rutl...@arm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
Acked-by: Rob Herring r...@kernel.org
Acked-by: Christoffer Dall
From: Marc Zyngier marc.zyng...@arm.com
Add handlers for all the AArch32 debug registers that are accessible
from EL0 or EL1. The code follow the same strategy as the AArch64
counterpart with regards to tracking the dirty state of the debug
registers.
Reviewed-by: Anup Patel
From: Marc Zyngier marc.zyng...@arm.com
Introduce the support code for emulating a GICv2 on top of GICv3
hardware.
Acked-by: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/kvm_asm.h | 2 +
arch/arm64/kvm/vgic-v3-switch.S |
The following changes since commit 33b458d276bbdbe28febac0742835002b9f4778d:
KVM: SVM: Fix CPL export via SS.DPL (2014-06-30 16:45:28 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to
Hi Paolo,
On Fri, Aug 01, 2014 at 11:05:13AM +0200, Paolo Bonzini wrote:
Il 01/08/2014 10:09, Wanpeng Li ha scritto:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for
Il 04/08/2014 12:11, Wanpeng Li ha scritto:
Hi Paolo,
On Fri, Aug 01, 2014 at 11:05:13AM +0200, Paolo Bonzini wrote:
Il 01/08/2014 10:09, Wanpeng Li ha scritto:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the
On Thu, Jul 10, 2014 at 07:42:31AM -0700, Christoffer Dall wrote:
When userspace loads code and data in a read-only memory regions, KVM
needs to be able to handle this on arm and arm64. Specifically this is
used when running code directly from a read-only flash device; the
common scenario is
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for certain VMM.
We map virtual APIC page address and TPR threshold from L1 VMCS. If
TPR_BELOW_THRESHOLD VM exit is
On Mon, Aug 04, 2014 at 12:13:13PM +0200, Paolo Bonzini wrote:
Il 04/08/2014 12:11, Wanpeng Li ha scritto:
Hi Paolo,
On Fri, Aug 01, 2014 at 11:05:13AM +0200, Paolo Bonzini wrote:
Il 01/08/2014 10:09, Wanpeng Li ha scritto:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
This patch enables irqfd on ARM.
irqfd framework enables to inject a virtual IRQ into a guest upon an
eventfd trigger. User-side uses KVM_IRQFD VM ioctl to provide KVM with
a kvm_irqfd struct that associates a VM, an eventfd, an IRQ number
(aka. the gsi). When an actor signals the eventfd
On Fri, Aug 01, 2014 at 10:48:36AM +0100, Alex Bennée wrote:
Christoffer Dall writes:
On Thu, Jul 31, 2014 at 05:45:28PM +0100, Peter Maydell wrote:
On 31 July 2014 17:38, Christoffer Dall christoffer.d...@linaro.org
wrote:
If we are not complaining when setting the pause value to
On Fri, Aug 01, 2014 at 10:11:52AM +0100, Alex Bennée wrote:
Christoffer Dall writes:
On Thu, Jul 31, 2014 at 04:14:51PM +0100, Alex Bennée wrote:
Christoffer Dall writes:
On Wed, Jul 09, 2014 at 02:55:12PM +0100, Alex Bennée wrote:
To cleanly restore an SMP VM we need to
On Thu, Jul 31, 2014 at 07:21:44PM +0200, Paolo Bonzini wrote:
Il 31/07/2014 19:04, Peter Maydell ha scritto:
On 31 July 2014 17:57, Paolo Bonzini pbonz...@redhat.com wrote:
Il 09/07/2014 15:55, Alex Bennée ha scritto:
To cleanly restore an SMP VM we need to ensure that the current pause
Christoffer Dall writes:
On Thu, Jul 31, 2014 at 07:21:44PM +0200, Paolo Bonzini wrote:
Il 31/07/2014 19:04, Peter Maydell ha scritto:
On 31 July 2014 17:57, Paolo Bonzini pbonz...@redhat.com wrote:
Il 09/07/2014 15:55, Alex Bennée ha scritto:
snip
No, it's not. It's just the state of
Il 02/08/2014 06:15, Xiao Guangrong ha scritto:
I prefer to also caching the spte’s generation number, then check the number
in quickly_check_mmio_pf().
I agree, thanks Xiao for the review and David for the report!
Paolo
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To unsubscribe from this list: send the line unsubscribe kvm in
the
Il 01/08/2014 10:12, Wanpeng Li ha scritto:
+int kvm_lapic_ack_apicv(struct kvm_vcpu *vcpu)
+{
+ struct kvm_lapic *apic = vcpu-arch.apic;
+ int vec;
+
+ vec = kvm_apic_has_interrupt(vcpu);
+
+ if (vec == -1)
+ return vec;
+
+ apic_set_vector(vec,
Il 01/08/2014 10:12, Wanpeng Li ha scritto:
External interrupt will cause L1 vmexit w/ reason external interrupt when L2
is
running. Then L1 will pick up the interrupt through vmcs12 if L1 set the ack
interrupt bit. Commit 77b0f5d (KVM: nVMX: Ack and write vector info to
intr_info
if L1
Il 04/08/2014 12:58, Wanpeng Li ha scritto:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for certain VMM.
We map virtual APIC page address and TPR threshold from
I will be on vacation next week. I don't expect any big problems since
I'll send the ARM and PPC patches to Linus no later than Thursday.
I will not merge any more x86 patches for the merge window.
Paolo
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the body of a message
On 10 July 2014 16:50, Alex Bennée alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
When we have a problem syncing CP registers between kvm-qemu it's a
lot more useful to have the names of the registers in the log than just
a random abort() and core dump.
Signed-off-by: Alex
On 10 July 2014 16:50, Alex Bennée alex.ben...@linaro.org wrote:
Before we launch a guest we query KVM for the list of co-processor
registers it knows about which is used later for save/restore of machine
state. The logic is identical for both 32-bit and 64-bit so I've moved
it all into the
On Thu, Jul 31, 2014 at 02:50:00PM +0300, Razya Ladelsky wrote:
Resubmitting the patch in: http://marc.info/?l=kvmm=140594903520308w=2
after fixing the whitespaces issues.
Thank you,
Razya
From f293e470b36ff9eb4910540c620315c418e4a8fc Mon Sep 17 00:00:00 2001
Above should come
The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current
systems. Rather than just add a bit it seems like a good time to also set
things at run-time instead of compile time to accomodate more hardware.
This patch sets TCR_EL2.PS, VTCR_EL2.T0SZ and vttbr_baddr_mask in runtime,
Reset, this time with the right mailing lists.
Thanks to Markus for noticing.
Later, Juan.
Juan Quintela quint...@redhat.com wrote:
Hi
Please, send any topic that you are interested in covering.
Thanks, Juan.
Call details:
15:00 CEST
13:00 UTC
09:00 EDT
Every two weeks
By
Since this fixes a real problem and didn't make it into 3.16 it would be
good if this made it into 3.17.
-Joel
On 08/04/2014 09:38 AM, Joel Schopp wrote:
The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current
systems. Rather than just add a bit it seems like a good time
On Mon, Aug 04, 2014 at 09:42:46AM -0500, Joel Schopp wrote:
Since this fixes a real problem and didn't make it into 3.16 it would be
good if this made it into 3.17.
It's too late for the merge window, we have to review and test as I told
you in a private e-mail.
We will review this and test
On Mon, Aug 4, 2014 at 5:44 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 02/08/2014 06:15, Xiao Guangrong ha scritto:
I prefer to also caching the spte’s generation number, then check the number
in quickly_check_mmio_pf().
I agree, thanks Xiao for the review and David for the report!
I
From: Christian Borntraeger borntrae...@de.ibm.com
For lots of exits the min time (and sometimes max) is 0 or 1. Lets
increase the accurancy similar to what the average field alread does.
Signed-off-by: Christian Borntraeger borntrae...@de.ibm.com
Acked-by: David Ahern dsah...@gmail.com
Cc:
Hi Ingo,
Mostly fixes plus some refactoring work, more to come as I process
Adrian Hunter big patch set and other that missed this pull request.
Please consider pulling,
- Arnaldo
The following changes since commit f9b9f812235d53f774a083e88a5a23b517a69752:
Merge tag
https://bugzilla.kernel.org/show_bug.cgi?id=53361
Chris Harrington ironiri...@gmail.com changed:
What|Removed |Added
CC|
On 08/02/2014 01:35 AM, Paolo Bonzini wrote:
Il 01/08/2014 23:09, Chris J Arges ha scritto:
Hi,
We are planning on running kvm-unit-tests as part of our test suite; but
I've noticed that many tests fail (even running the latest kvm tip).
After searching I found many BZ entires that seem to
Il 04/08/2014 19:02, Chris J Arges ha scritto:
Paulo,
Hopefully this is enough to get started; I can file this as a bug if its
easier to track. Let me know if there is additional information that is
needed. I'm thinking some may be userspace qemu-system-x86_64 issues
since three of them can
On 08/04/2014 01:20 PM, Paolo Bonzini wrote:
Il 04/08/2014 19:02, Chris J Arges ha scritto:
Paulo,
Hopefully this is enough to get started; I can file this as a bug if its
easier to track. Let me know if there is additional information that is
needed. I'm thinking some may be userspace
Il 04/08/2014 20:37, Chris J Arges ha scritto:
Paolo,
Yes this is how I initially ran the script:
./configure make
sudo ./run_tests.sh -v
Then if any commands that failed, I re-ran the command it output in
order to show more output here for debugging.
Which tests are failing and which
On 08/04/2014 01:40 PM, Paolo Bonzini wrote:
Il 04/08/2014 20:37, Chris J Arges ha scritto:
Paolo,
Yes this is how I initially ran the script:
./configure make
sudo ./run_tests.sh -v
Then if any commands that failed, I re-ran the command it output in
order to show more output here for
On Fri, 2014-08-01 at 16:12 +0800, Wanpeng Li wrote:
External interrupt will cause L1 vmexit w/ reason external interrupt when L2
is
running. Then L1 will pick up the interrupt through vmcs12 if L1 set the ack
interrupt bit. Commit 77b0f5d (KVM: nVMX: Ack and write vector info to
Use the kernel hashtable interface instead of the hlist interface.
This allows us to eliminate some unneeded code and make the code
simpler.
Signed-off-by: Sasha Levin sasha.le...@oracle.com
---
arch/x86/include/asm/kvm_host.h |4 ++--
arch/x86/kvm/mmu.c | 16 ++--
The following events can lead to an incorrect KVM_EXIT_MMIO bubbling
up to userspace:
(1) Guest accesses gpa X without a memory slot. The gfn is cached in
struct kvm_vcpu_arch (mmio_gfn). On Intel EPT-enabled hosts, KVM sets
the SPTE write-execute-noread so that future accesses cause
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