Wanpeng Li wrote on 2014-08-04:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for certain VMM.
We map virtual APIC page address and TPR threshold from L1 VMCS. If
The __ARM64_SYS_REG() macro is already defined in uapi/asm/kvm.h
of Linux-3.16-rcX hence remove it from arm/aarch64/kvm-cpu.c
Signed-off-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Anup Patel anup.pa...@linaro.org
---
tools/kvm/arm/aarch64/kvm-cpu.c | 11 ---
1
This patchset updates KVMTOOL to use some of the features
supported by Linux-3.16 KVM ARM/ARM64, such as:
1. Target CPU == Host using KVM_ARM_PREFERRED_TARGET vm ioctl
2. Target CPU type Potenza for using KVMTOOL on X-Gene
3. PSCI v0.2 support for Aarch32 and Aarch64 guest
4. System event exit
Instead, of trying out each and every target type we should use
KVM_ARM_PREFERRED_TARGET vm ioctl to determine target type
for KVM ARM/ARM64.
We bail-out target type returned by KVM_ARM_PREFERRED_TARGET vm ioctl
is not known to kvmtool.
Signed-off-by: Pranavkumar Sawargaonkar
If in-kernel KVM support PSCI-0.2 emulation then we should set
KVM_ARM_VCPU_PSCI_0_2 feature for each guest VCPU and also
provide arm,psci-0.2,arm,psci as PSCI compatible string.
This patch updates kvm_cpu__arch_init() and setup_fdt() as
per above.
Signed-off-by: Pranavkumar Sawargaonkar
The VCPU target type KVM_ARM_TARGET_XGENE_POTENZA is available
in latest Linux-3.16-rcX or higher hence register aarch64 target
type for it.
This patch enables us to run KVMTOOL on X-Gene Potenza host.
Signed-off-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Anup Patel
The KVM_EXIT_SYSTEM_EVENT exit reason was added to define
architecture independent system-wide events for a Guest.
Currently, it is used by in-kernel PSCI-0.2 emulation of
KVM ARM/ARM64 to inform user space about PSCI SYSTEM_OFF
or PSCI SYSTEM_RESET request.
For now, we simply treat all
On 5 August 2014 14:19, Anup Patel anup.pa...@linaro.org wrote:
This patchset updates KVMTOOL to use some of the features
supported by Linux-3.16 KVM ARM/ARM64, such as:
1. Target CPU == Host using KVM_ARM_PREFERRED_TARGET vm ioctl
2. Target CPU type Potenza for using KVMTOOL on X-Gene
3.
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h include file.
We also add #ifndef __ASSEMBLY__ in order to use asm/pmu.h from
assembly code.
Signed-off-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Pranavkumar Sawargaonkar
Full context switch of all PMU registers for both host and
guest can make KVM world-switch very expensive.
This patch improves current PMU context switch by implementing
lazy context switch of PMU registers.
To achieve this, we trap all PMU register accesses and use a
per-VCPU dirty flag to keep
This patch introduces common PMU IRQ routing code for
KVM ARM and KVM ARM64 under virt/kvm/arm directory.
The virtual PMU IRQ number for each Guest VCPU will be
provided by user space using set device address vm ioctl
with prameters:
dev_id = KVM_ARM_DEVICE_PMU
type = VCPU number
addr = PMU IRQ
A hypervisor will typically mask the overflow interrupt before
forwarding it to Guest Linux hence we need to re-enable the overflow
interrupt after clearing it in Guest Linux. Also, this re-enabling
of overflow interrupt does not harm in non-virtualized scenarios.
Signed-off-by: Pranavkumar
This patchset enables PMU virtualization in KVM ARM64. The
Guest can now directly use PMU available on the host HW.
The virtual PMU IRQ injection for Guest VCPUs is managed by
small piece of code shared between KVM ARM and KVM ARM64. The
virtual PMU IRQ number will be based on Guest machine model
A hypervisor will typically mask the overflow interrupt before
forwarding it to Guest Linux hence we need to re-enable the overflow
interrupt after clearing it in Guest Linux. Also, this re-enabling
of overflow interrupt does not harm in non-virtualized scenarios.
Signed-off-by: Pranavkumar
This patch implements following stuff:
1. Save/restore all PMU registers for both Guest and Host in
KVM world switch.
2. Reserve last PMU event counter for performance analysis in
EL2-mode. To achieve we fake the number of event counters available
to the Guest by trapping PMCR_EL0 register
On 5 August 2014 15:02, Anup Patel apa...@apm.com wrote:
On Tue, Aug 5, 2014 at 2:54 PM, Anup Patel anup.pa...@linaro.org wrote:
This patchset enables PMU virtualization in KVM ARM64. The
Guest can now directly use PMU available on the host HW.
The virtual PMU IRQ injection for Guest VCPUs is
On Tue, Aug 5, 2014 at 2:54 PM, Anup Patel anup.pa...@linaro.org wrote:
This patchset enables PMU virtualization in KVM ARM64. The
Guest can now directly use PMU available on the host HW.
The virtual PMU IRQ injection for Guest VCPUs is managed by
small piece of code shared between KVM ARM
Il 04/08/2014 19:02, Chris J Arges ha scritto:
All tests below are done with the kvm tip (fresh as of today) merged
with 3.16-rc4.
Sorry, I had missed the list of failures.
* Failures:
- pmu
As suggested in comment 2 on this bug:
https://bugzilla.redhat.com/show_bug.cgi?id=1079796
Adding
vPMU is only available with -cpu host, and so is TSC_ADJUST because
the QEMU CPU models forgot about it.
Adjust these two tests to use the option.
Reported-by: Chris J Arges chris.j.ar...@canonical.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/unittests.cfg | 2 ++
1 file
The APICBASE register is already tested by the apic testcase,
and the simple-minded tests in msr.flat actually trigger a
general protection fault nowadays. Just drop the tests, and
the test now passes.
Reported-by: Chris J Arges chris.j.ar...@canonical.com
Signed-off-by: Paolo Bonzini
3.16 (guest hangs with two rng devices)
3.16 + quick fix (can startup with two rng devices) (hotplug issue 1 + hotplug
issue 2 exist)
lates torvalds/linux.git + amit 4 patches (can startup with two rng devices)
(only hotplug issue 2 exists)
However, the 4 patches also fixed the hang issue, the
The test was trying to set CR0.PG, not clear it (and it was
already set, even).
Reported-by: Chris J Arges chris.j.ar...@canonical.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/pcid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/pcid.c b/x86/pcid.c
index
Commit 29577fc00ba4 (KVM: PPC: HV: Remove generic instruction emulation)
caused a build failure:
arch/powerpc/kvm/kvm-pr.o:(__tracepoints+0xa8): multiple definition of
`__tracepoint_kvm_ppc_instr'
arch/powerpc/kvm/kvm.o:(__tracepoints+0x1c0): first defined here
due to a duplicate definition of
Add KVM Book3e AltiVec support and enable e6500 core.
Changes:
v3:
- use distinct SPE/AltiVec exception handlers
- make ONE_REG AltiVec support powerpc generic
- add ONE_REG IVORs support
v2:
- integrate Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue
in January and take into
Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- use distinct SPE/AltiVec
Make ONE_REG AltiVec support common across server and embedded implementations
moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
-
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2-v3:
- no changes
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index
Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- new patch
arch/powerpc/include/uapi/asm/kvm.h | 24 +++
arch/powerpc/kvm/booke.c| 132
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no changes
v2:
- remove
Il 05/08/2014 09:56, Zhang, Yang Z ha scritto:
Wanpeng Li wrote on 2014-08-04:
This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
TPR shadow/threshold feature is important to speed up the Windows guest.
Besides, it is a must feature for certain VMM.
We map virtual APIC
Il 05/08/2014 06:42, Wanpeng Li ha scritto:
After commit 77b0f5d (KVM: nVMX: Ack and write vector info to intr_info
if L1 asks us to), Acknowledge interrupt on exit behavior can be
emulated. To do so, KVM will ask the APIC for the interrupt vector if
during a nested vmexit if
On 2014/8/5 17:49, Michael S. Tsirkin wrote:
On Tue, Aug 05, 2014 at 02:29:28PM +0800, Zhangjie (HZ) wrote:
Jason is right, the new order is not the cause of network unreachable.
Changing order seems not work. After about 40 times, the problem occurs
again.
Maybe there is other hidden
Il 30/06/2014 12:51, Paul Mackerras ha scritto:
This series of patches provides a way to implement IRQFD support
without having to implement IRQ routing, and adds IRQFD support for
the XICS interrupt controller emulation. (XICS is the interrupt
controller defined for the pSeries machine type,
Il 05/08/2014 12:35, Paolo Bonzini ha scritto:
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index e96b50d0bdab..2325168ad1ff 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -300,3 +300,5 @@ int kvmppc_emulate_instruction(struct kvm_run *run,
Hi,
On 08/05/2014 01:04 PM, Paolo Bonzini wrote:
Il 05/08/2014 06:42, Wanpeng Li ha scritto:
After commit 77b0f5d (KVM: nVMX: Ack and write vector info to intr_info
if L1 asks us to), Acknowledge interrupt on exit behavior can be
emulated. To do so, KVM will ask the APIC for the interrupt
On Tue, Aug 05, 2014 at 02:39:05PM +0200, Felipe Reyes wrote:
Hi,
On 08/05/2014 01:04 PM, Paolo Bonzini wrote:
Il 05/08/2014 06:42, Wanpeng Li ha scritto:
After commit 77b0f5d (KVM: nVMX: Ack and write vector info to intr_info
if L1 asks us to), Acknowledge interrupt on exit behavior can be
Hi,
Each vCPU has its own TSC. A desirable property of such a system is that
the TSCs of all of the vCPUs in a VM are exactly synchronized.
If the TSCs are exactly synchronized, when software reads the TSC of vCPU A and
then reads the TSC of vCPU B,
the read on B is guaranteed to be a larger
Juan Quintela quint...@redhat.com wrote:
Reset, this time with the right mailing lists.
Thanks to Markus for noticing.
Later, Juan.
Juan Quintela quint...@redhat.com wrote:
No agenda, no call. Sorry for the late advice :-(
Later, Juan.
--
To unsubscribe from this list: send the line
On Tue, Jul 08, 2014 at 12:09:01PM +0100, Marc Zyngier wrote:
So far, all the VGIC data structures are statically defined by the
*maximum* number of vcpus and interrupts it supports. It means that
we always have to oversize it to cater for the worse case.
Start by changing the data
On Tue, Jul 08, 2014 at 12:09:02PM +0100, Marc Zyngier wrote:
Having a dynamic number of supported interrupts means that we
cannot relly on VGIC_NR_SHARED_IRQS being fixed anymore.
Instead, make it take the distributor structure as a parameter,
so it can return the right value.
On Tue, Jul 08, 2014 at 12:09:05PM +0100, Marc Zyngier wrote:
Nuke VGIC_NR_IRQS entierly, now that the distributor instance
contains the number of IRQ allocated to this GIC.
Also add VGIC_NR_IRQS_LEGACY to preserve the current API.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
On Tue, Jul 08, 2014 at 12:09:04PM +0100, Marc Zyngier wrote:
Now that we can (almost) dynamically size the number of interrupts,
we're facing an interesting issue:
We have to evaluate at runtime whether or not an access hits a valid
register, based on the sizing of this particular instance
On 08/04/2014 07:35 PM, Mathew Li wrote:
Hi,
I have a quick question. How do we add a hard disk to the qemu ARM VM?
I tried:
qemu-system-aarch64 -machine virt -hda disk.img -kernel image -initrd
initrd.img
qemu-system-aarch64 -machine virt -sd disk.img -kernel image -initrd
On Tue, Jul 08, 2014 at 12:09:03PM +0100, Marc Zyngier wrote:
We now have the information about the number of CPU interfaces in
the distributor itself. Let's get rid of VGIC_MAX_CPUS, and just
rely on KVM_MAX_VCPUS where we don't have the choice. Yet.
Signed-off-by: Marc Zyngier
We currently track the pid of the task that runs the VCPU in
vcpu_load. Since we call vcpu_load for all kind of ioctls on a
CPU, this causes hickups due to synchronize_rcu if one CPU is
modified by another CPU or the main thread (e.g. initialization,
reset). We track the pid only for the purpose
On Tue, Aug 05, 2014 at 12:26:26PM +0200, Paolo Bonzini wrote:
Il 04/08/2014 19:02, Chris J Arges ha scritto:
All tests below are done with the kvm tip (fresh as of today) merged
with 3.16-rc4.
Sorry, I had missed the list of failures.
* Failures:
- pmu
As suggested in comment 2 on
On Tue, Jul 08, 2014 at 12:09:07PM +0100, Marc Zyngier wrote:
In order to make the number of interrupt configurable, use the new
interrupts
fancy device management API to add KVM_DEV_ARM_VGIC_GRP_NR_IRQS as
a VGIC configurable attribute.
Userspace can now
On Tue, Jul 08, 2014 at 12:09:06PM +0100, Marc Zyngier wrote:
It is now quite easy to delay the allocation of the vgic tables
until we actually require it to be up and running (when the first
the first starting ?
starting to kick around).
This allow us to allocate memory for the exact
On Tue, Jul 08, 2014 at 12:09:08PM +0100, Marc Zyngier wrote:
The GIC CPU interface is always 4k aligned. If the host is using
64k pages, it is critical to place the guest's GICC interface at the
same relative alignment as the host's GICV. Failure to do so results
in an impossibility for the
When we try to hot-remove a busy virtio-rng device from QEMU monitor,
the device can't be hot-removed. Because virtio-rng driver hangs at
wait_for_completion_killable().
This patch fixed the hang by completing have_data completion before
unregistering a virtio-rng device.
Signed-off-by: Amos
On Tue, Aug 05, 2014 at 06:28:54PM +0800, Amos Kong wrote:
3.16 (guest hangs with two rng devices)
3.16 + quick fix (can startup with two rng devices) (hotplug issue 1 +
hotplug issue 2 exist)
lates torvalds/linux.git + amit 4 patches (can startup with two rng devices)
(only hotplug issue 2
On 08/05/2014 05:26 AM, Paolo Bonzini wrote:
Il 04/08/2014 19:02, Chris J Arges ha scritto:
All tests below are done with the kvm tip (fresh as of today) merged
with 3.16-rc4.
Updated information with the three new kvm-unit-tests patches you've posted.
Sorry, I had missed the list of
On Mon, Aug 4, 2014 at 5:31 PM, Wanpeng Li wanpeng...@linux.intel.com wrote:
Hi David,
On Mon, Aug 04, 2014 at 02:10:20PM -0700, David Matlack wrote:
The following events can lead to an incorrect KVM_EXIT_MMIO bubbling
up to userspace:
(1) Guest accesses gpa X without a memory slot. The gfn is
On Mon, 2014-08-04 at 22:41 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:23 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-...@vger.kernel.org; kvm@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
On Mon, Aug 4, 2014 at 8:36 PM, Xiao Guangrong
xiaoguangr...@linux.vnet.ibm.com wrote:
On 08/05/2014 05:10 AM, David Matlack wrote:
This patch fixes the issue by doing the following:
- Tag the mmio cache with the memslot generation and use it to
validate mmio cache lookups.
- Extend
From: Gavin Shan gws...@linux.vnet.ibm.com
The VFIO related components could be built as dynamic modules.
Unfortunately, CONFIG_EEH can't be configured to m. The patch
fixes the build errors when configuring VFIO related components
as dynamic modules as follows:
CC [M]
This adds necessary declarations to the module, otherwise multiple
dynamic linker errors happen:
vfio_spapr_eeh: Unknown symbol eeh_pe_set_option (err 0)
vfio_spapr_eeh: Unknown symbol eeh_pe_configure (err 0)
vfio_spapr_eeh: Unknown symbol eeh_pe_reset (err 0)
vfio_spapr_eeh: Unknown symbol
The existing vfio_pci_open() fails if there is no EEH support for PCI.
This breaks POWER7's P5IOC2 PHB support which this patch brings back.
It is a warning because this should not normally happen on supported
configurations such as POWER8+IODA so we always want to see it in dmesg.
It is _once()
Here is what I have in my stash which would be nice to have in 3.17.
Alexey Kardashevskiy (2):
vfio_spapr_eeh: Enable compile as a module
vfio_pci: spapr: Enable VFIO if EEH is not supported
Gavin Shan (2):
powerpc/eeh: Export eeh_iommu_group_to_pe()
vfio: spapr: Fix build error
From: Gavin Shan gws...@linux.vnet.ibm.com
The function is used by VFIO driver, which might be built as a
dynamic module.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/eeh.c
On Wed, 2014-08-06 at 12:48 +1000, Alexey Kardashevskiy wrote:
From: Gavin Shan gws...@linux.vnet.ibm.com
The VFIO related components could be built as dynamic modules.
Unfortunately, CONFIG_EEH can't be configured to m. The patch
fixes the build errors when configuring VFIO related
On 08/06/2014 06:39 AM, David Matlack wrote:
On Mon, Aug 4, 2014 at 8:36 PM, Xiao Guangrong
xiaoguangr...@linux.vnet.ibm.com wrote:
On 08/05/2014 05:10 AM, David Matlack wrote:
This patch fixes the issue by doing the following:
- Tag the mmio cache with the memslot generation and use it to
On Wed, 2014-08-06 at 12:48 +1000, Alexey Kardashevskiy wrote:
The existing vfio_pci_open() fails if there is no EEH support for PCI.
This breaks POWER7's P5IOC2 PHB support which this patch brings back.
It is a warning because this should not normally happen on supported
configurations such
On Tue, Aug 05, 2014 at 09:12:50PM -0600, Alex Williamson wrote:
On Wed, 2014-08-06 at 12:48 +1000, Alexey Kardashevskiy wrote:
From: Gavin Shan gws...@linux.vnet.ibm.com
The VFIO related components could be built as dynamic modules.
Unfortunately, CONFIG_EEH can't be configured to m. The
On Tue, 2014-08-05 at 21:44 -0600, Alex Williamson wrote:
ret = vfio_spapr_pci_eeh_open(vdev-pdev);
- if (ret) {
- vfio_pci_disable(vdev);
- goto error;
- }
+ if (ret)
+
Commit 29577fc00ba4 (KVM: PPC: HV: Remove generic instruction emulation)
caused a build failure:
arch/powerpc/kvm/kvm-pr.o:(__tracepoints+0xa8): multiple definition of
`__tracepoint_kvm_ppc_instr'
arch/powerpc/kvm/kvm.o:(__tracepoints+0x1c0): first defined here
due to a duplicate definition of
Add KVM Book3e AltiVec support and enable e6500 core.
Changes:
v3:
- use distinct SPE/AltiVec exception handlers
- make ONE_REG AltiVec support powerpc generic
- add ONE_REG IVORs support
v2:
- integrate Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue
in January and take into
Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- use distinct SPE/AltiVec
Make ONE_REG AltiVec support common across server and embedded implementations
moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
-
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2-v3:
- no changes
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index
Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- new patch
arch/powerpc/include/uapi/asm/kvm.h | 24 +++
arch/powerpc/kvm/booke.c| 132
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no changes
v2:
- remove
Il 30/06/2014 12:51, Paul Mackerras ha scritto:
This series of patches provides a way to implement IRQFD support
without having to implement IRQ routing, and adds IRQFD support for
the XICS interrupt controller emulation. (XICS is the interrupt
controller defined for the pSeries machine type,
Il 05/08/2014 12:35, Paolo Bonzini ha scritto:
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index e96b50d0bdab..2325168ad1ff 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -300,3 +300,5 @@ int kvmppc_emulate_instruction(struct kvm_run *run,
On Mon, 2014-08-04 at 22:41 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:23 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
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