GCC doesn't warn that ((u32)e-index 24) == 0x800 is always false?
I think SDM says '(e-index 8) == 0x8'.
Missed that. Thank you.
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Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of it.
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Will send fixed patch this evening.
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On Wed, 2014-12-10 at 15:42 +0800, Thomas Lau wrote:
I briefly tested Penryn, Westmere. Bug still could reproduce.
It should be four parameters printed on the screen, right below
the error code string. Could you please post them?
how could I set level, model and enforce on libvirt ?! I
Two minor fixes for emulation of instructions on VM86.
Thanks for reviewing them.
Nadav Amit (2):
KVM: x86: Do not push eflags.vm on pushf
KVM: x86: Emulate should check #UD before #GP
arch/x86/kvm/emulate.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
--
1.9.1
Intel SDM table 6-2 (Priority Among Simultaneous Exceptions and Interrupts)
shows that faults from decoding the next instruction got higher priority than
general protection. Moving the protected-mode check before the CPL check to
avoid wrong exception on vm86 mode.
Signed-off-by: Nadav Amit
The pushf instruction does not push eflags.VM, so emulation should not do so as
well. Although eflags.RF should not be pushed as well, it is already cleared
by the time pushf is executed.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/emulate.c | 2 +-
1 file changed, 1
Hi all,
On Wed, Dec 10, 2014 at 08:07:45AM -0100, Eugene Korenevsky wrote:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of
On Wed, Dec 10, 2014 at 08:13:58AM -0100, Eugene Korenevsky wrote:
Will send fixed patch this evening.
Please see my reply to another thread.
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2014-12-10 17:01 GMT+08:00 Wanpeng Li wanpeng...@linux.intel.com:
Hi all,
On Wed, Dec 10, 2014 at 08:07:45AM -0100, Eugene Korenevsky wrote:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a
Eugene Korenevsky ekorenev...@gmail.com writes:
Hi, Eugene, is it okay to split my part up?
I think the patch is atomic. No ideas how this patch could be split
without breaking its integrity.
You are a co-author of the patch since your ideas make significant part of it.
I was suggesting
Hi Christoffer,
Reviewed-by: Eric Auger eric.au...@linaro.org
see few comments below.
On 12/09/2014 04:44 PM, Christoffer Dall wrote:
From: Peter Maydell peter.mayd...@linaro.org
VGIC initialization currently happens in three phases:
(1) kvm_vgic_create() (triggered by userspace GIC
On 12/09/2014 04:44 PM, Christoffer Dall wrote:
Some code paths will need to check to see if the internal state of the
vgic has been initialized (such as when creating new VCPUs), so
introduce such a macro that checks the nr_cpus field which is set when
the vgic has been initialized.
Also
On 06/12/2014 04:03, Andy Lutomirski wrote:
paravirt_enabled has the following effects:
- Disables the F00F bug workaround warning. There is no F00F bug
workaround any more because Linux's standard IDT handling already
works around the F00F bug, but the warning still exists. This
On 07/12/2014 10:49, Nadav Amit wrote:
The macro GP already sets the flag Prefix. Remove the redundant flag for
0f_38_f0 and 0f_38_f1 opcodes.
Signed-off-by: Nadav Amit na...@cs.technion.ac.il
---
arch/x86/kvm/emulate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On 10/12/2014 10:19, Nadav Amit wrote:
Two minor fixes for emulation of instructions on VM86.
Thanks for reviewing them.
Nadav Amit (2):
KVM: x86: Do not push eflags.vm on pushf
KVM: x86: Emulate should check #UD before #GP
arch/x86/kvm/emulate.c | 14 +++---
1 file
On 06/12/2014 16:02, Bandan Das wrote:
If L0 has disabled EPT, don't advertise unrestricted
mode at all since it depends on EPT to run real mode code.
Signed-off-by: Bandan Das b...@redhat.com
---
arch/x86/kvm/vmx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On 12/09/2014 04:44 PM, Christoffer Dall wrote:
When the vgic initializes its internal state it does so based on the
number of VCPUs available at the time. If we allow KVM to create more
VCPUs after the VGIC has been initialized, we are likely to error out in
unfortunate ways later, perform
On 12/09/2014 04:44 PM, Christoffer Dall wrote:
Userspace assumes that it can wire up IRQ injections after having
created all VCPUs and after having created the VGIC, but potentially
before starting the first VCPU. This can currently lead to lost IRQs
because the state of that IRQ injection
On 08/12/2014 04:18, nick wrote:
Paolo,
Not to be annoying but I am wondering, if my patch has been merged as I have
yet to see it in the mainline
kernel.
It will be sent to Linus during the merge window.
Paolo
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Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
linux-headers/asm-x86/kvm.h |5 +
linux-headers/linux/kvm.h | 14 +++---
2 files changed, 8 insertions(+), 11 deletions(-)
Index: qemu/linux-headers/asm-x86/kvm.h
Add machine option and QMP commands to configure TSC deadline
timer advancement.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
monitor.c | 15 ++
qapi-schema.json | 29 +++
qmp-commands.hx | 48
target-i386/kvm.c
Add command to set TSC deadline timer advancement.
This value will be subtracted from the expiration time
of the high resolution timer which emulates
TSC deadline timer.
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More
On 09/12/2014 03:49, Tian, Kevin wrote:
- Now we have XenGT/KVMGT separately maintained, and KVMGT lags
behind XenGT regarding to features and qualities. Likely you'll continue
see stale code (like Xen inst decoder) for some time. In the future we
plan to maintain a single kernel repo for
kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm/arch/x86/include/asm/kvm_host.h
===
--- kvm.orig/arch/x86/include/asm/kvm_host.h
See patches for details.
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On 10/12/2014 17:23, Marcelo Tosatti wrote:
Add machine option and QMP commands to configure TSC deadline
timer advancement.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
monitor.c | 15 ++
qapi-schema.json | 29 +++
qmp-commands.hx |
See patches for details.
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For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any scenario
which requires strict timing regarding timer
On 12/10/2014 12:06 PM, Marcelo Tosatti wrote:
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any
On 12/10/2014 12:06 PM, Marcelo Tosatti wrote:
kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Is that good? Bad? How does this patch address the issue?
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On Wed, Dec 10, 2014 at 12:10:04PM -0500, Rik van Riel wrote:
On 12/10/2014 12:06 PM, Marcelo Tosatti wrote:
kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Is that good? Bad? How does this patch address the issue?
What issue?
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On Wed, Dec 10, 2014 at 06:09:19PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:04, Marcelo Tosatti wrote:
Please add an object property to the x86 CPU object. It can then be
configured with -global on the command line.
Don't want to allow individual values for different CPUs.
It
On Wed, Dec 10, 2014 at 06:10:19PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:06, Marcelo Tosatti wrote:
See patches for details.
Difference between v1 and v2? Please fix your workflow.
Paolo
Wrong sender email address, that is all.
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https://bugzilla.kernel.org/show_bug.cgi?id=87611
Alan a...@lxorguk.ukuu.org.uk changed:
What|Removed |Added
CC||a...@lxorguk.ukuu.org.uk
On Wed, Dec 10, 2014 at 06:01:21PM +0100, Paolo Bonzini wrote:
On 10/12/2014 17:23, Marcelo Tosatti wrote:
Add machine option and QMP commands to configure TSC deadline
timer advancement.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
monitor.c | 15
On 10/12/2014 17:53, marcelo.tosa...@amt.cnet wrote:
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any
On 10/12/2014 18:04, Marcelo Tosatti wrote:
Please add an object property to the x86 CPU object. It can then be
configured with -global on the command line.
Don't want to allow individual values for different CPUs.
It is a per-VM property.
Why? It can cause busy waiting, it would make
On 10/12/2014 18:27, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 06:09:19PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:04, Marcelo Tosatti wrote:
Please add an object property to the x86 CPU object. It can then be
configured with -global on the command line.
Don't want to allow
On Wed, Dec 10, 2014 at 06:08:14PM +0100, Paolo Bonzini wrote:
On 10/12/2014 17:53, marcelo.tosa...@amt.cnet wrote:
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to
On Tue, 2 Dec 2014 14:00:13 +0100
Cornelia Huck cornelia.h...@de.ibm.com wrote:
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 070006c..23d713b 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -51,6 +51,17 @@ extern
On Tue, 2 Dec 2014 14:00:26 +0100
Cornelia Huck cornelia.h...@de.ibm.com wrote:
Devices may support different sets of feature bits depending on which
revision they're operating at. Let's give the transport a way to
re-query the device about its features when the revision has been
changed.
https://bugzilla.kernel.org/show_bug.cgi?id=87611
--- Comment #1 from Antti Tönkyrä daeda...@pingtimeout.net ---
I also posted the patch to LKML but I think no-one picked it up and I didn't
have time to follow up on this after that. ( https://lkml.org/lkml/2014/11/9/57
)
--
You are receiving
On 12/10/2014 09:23 AM, Marcelo Tosatti wrote:
Add machine option and QMP commands to configure TSC deadline
timer advancement.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
+##
+# @get-lapic-tscdeadline-advance
+#
+# This command gets the TSC deadline timer advancement.
+#
On 10/12/2014 18:06, Marcelo Tosatti wrote:
See patches for details.
Difference between v1 and v2? Please fix your workflow.
Paolo
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For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any scenario
which requires strict timing regarding timer
kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm/arch/x86/include/asm/kvm_host.h
===
--- kvm.orig/arch/x86/include/asm/kvm_host.h
On 12/10/2014 12:27 PM, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 12:10:04PM -0500, Rik van Riel wrote:
On 12/10/2014 12:06 PM, Marcelo Tosatti wrote:
kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Is that good? Bad? How does this patch address
On 10/12/2014 18:34, Marcelo Tosatti wrote:
Let's start with a kvm-unit-tests patch to measure this value.
I can, but kvm-unit-test register state will not be similar to
actual guest state (think host/guest state loading).
7us is about 2 clock cycles. A lightweight vmexit is an order
On 10/12/2014 18:35, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 06:29:43PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:27, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 06:09:19PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:04, Marcelo Tosatti wrote:
Please add an object property
On Wed, Dec 10, 2014 at 12:50:29PM -0500, Rik van Riel wrote:
On 12/10/2014 12:27 PM, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 12:10:04PM -0500, Rik van Riel wrote:
On 12/10/2014 12:06 PM, Marcelo Tosatti wrote:
kvm_x86_ops-test_posted_interrupt() returns true/false depending
On Wed, Dec 10, 2014 at 06:29:43PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:27, Marcelo Tosatti wrote:
On Wed, Dec 10, 2014 at 06:09:19PM +0100, Paolo Bonzini wrote:
On 10/12/2014 18:04, Marcelo Tosatti wrote:
Please add an object property to the x86 CPU object. It can then be
2014-12-10 18:55+0100, Paolo Bonzini:
Well, my preferred choice would be automatic adjustment with a module
parameter. If we need manual tuning, per-CPU would be my choice, but
automatic is nicer anyway. :)
I agree with Paolo, and think it would be better not to touch QEMU ...
it makes little
On 10/12/2014 19:39, Radim Krčmář wrote:
2014-12-10 18:55+0100, Paolo Bonzini:
Well, my preferred choice would be automatic adjustment with a module
parameter. If we need manual tuning, per-CPU would be my choice, but
automatic is nicer anyway. :)
I agree with Paolo, and think it would
This series adds support for aarch64 to the kvm-unit-tests framework,
bringing it to the same level as the arm support. In the process a
few tweaks to the arm support were made, as one of the main goals
was to share as much code as possible between the two.
Patches
01 : A fix for the script
Implement asm_mmu_enable and flush_tlb_all, and then make a final
change to mmu.c in order to link it into arm64. The final change
is to map the code read-only. This is necessary because armv8
forces all writable code shared between EL1 and EL0 to be PXN.
Signed-off-by: Andrew Jones
When $ARCH != $TEST_DIR we should look there too. This patch cheats
though and makes cscope always look there, but then gets rid of the
duplicates generated when $ARCH == $TEST_DIR.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Makefile | 4 ++--
1 file changed, 2 insertions(+), 2
Separate the concepts of an 'svc', the syscall instruction present
on both arm and arm64, and 'svc mode', which is arm's kernel mode,
and doesn't exist on arm64. kernel mode on arm64 is modeled with
exception level 1 (el1).
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm/selftest.c|
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm/cstart64.S| 142 ++-
arm/selftest.c| 129 ---
arm/unittests.cfg | 2 -
config/config-arm64.mak | 1 +
lib/arm64/asm-offsets.c | 16
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm64/asm/page.h | 66 +++-
lib/arm64/asm/pgtable-hwdef.h | 136 ++
lib/arm64/asm/pgtable.h | 69 +
3 files changed, 270 insertions(+), 1 deletion(-)
To use page level descriptors we need some pgd/pud/pmd/pte
methods, and a few more flags defined.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm/asm/mmu.h | 16 +---
lib/arm/asm/pgtable-hwdef.h | 38 ++-
lib/arm/asm/pgtable.h | 91
* don't assume 1G PGDIR_SIZE or L1_CACHE_BYTES pgd alignment
* use page level descriptors for non-I/O memory
* apply new pgd/pud/pmd/pte methods
* split mmu.h to share function declarations
* use more generic flag names in mmu.c
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Using -kernel doesn't force qemu to exit immediately,
and thus we hang when trying to run arm/run. Using
-initrd works though.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm/run | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arm/run b/arm/run
index
Correct a type mismatch in the cpus initialization.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/arm/setup.c b/lib/arm/setup.c
index 5fa37ca35f383..50ca4cb9ff99e 100644
--- a/lib/arm/setup.c
+++
This changes the layout for arm too, but that's fine. The only
thing to keep in mind is that while arm64 will have a single
64k page for its stack, arm will have 16 4k pages. If the number
of stack pages matters, then unit tests that want to work for
both arm and arm64, may need to avoid using
This allows it to be different for arm64, even with setup.h
shared.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm/asm/mmu.h | 2 +-
lib/arm/asm/page.h | 5 ++---
lib/arm/asm/pgtable-hwdef.h | 6 ++
lib/arm/asm/setup.h | 6 ++
lib/arm/mmu.c
Files in lib/arm including asm/someheader.h will get
lib/arm/asm/someheader.h, not lib/asm/someheader.h. So we
need to use instead of in order to prepare for headers
of the same name, but for a different arch. We change all
'#include's of all arm files, as consistency looks better.
Drop the unused arguments from setup(), passing only the fdt.
This allows setup() to be more easily shared with arm64.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm/cstart.S| 12 ++--
lib/arm/setup.c | 3 +--
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git
A size_t can have a different size when compiled as
64-bit vs. 32-bit. When unsigned int is what we want,
then make sure unsigned int is what we use.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/chr-testdev.c | 4 ++--
lib/virtio.c | 2 +-
lib/virtio.h | 3 ++-
3 files
To test latency between TSC deadline timer
interrupt injection.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm-unit-tests/config/config-x86-common.mak
===
--- kvm-unit-tests.orig/config/config-x86-common.mak
This is the initial drop of the arm64 test framework and a first test
that just checks that setup completed (a selftest). kvm isn't needed
to run this test unless testing with smp 1.
Try it out with
yum install gcc-aarch64-linux-gnu
./configure --cross-prefix=aarch64-linux-gnu- --arch=arm64
On Wed, Dec 10, 2014 at 3:49 AM, Paolo Bonzini pbonz...@redhat.com wrote:
On 06/12/2014 04:03, Andy Lutomirski wrote:
paravirt_enabled has the following effects:
- Disables the F00F bug workaround warning. There is no F00F bug
workaround any more because Linux's standard IDT handling
See patches for details.
v2:
- fix email address.
v3:
- use module parameter for configuration of value (Paolo/Radim)
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kvm_x86_ops-test_posted_interrupt() returns true/false depending
whether 'vector' is set.
Next patch makes use of this interface.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm/arch/x86/include/asm/kvm_host.h
===
---
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any scenario
which requires strict timing regarding timer
In the interest of reduced future confusion, would it make sense to
drop the duplicate initialization for 3.20?
Yup. It would be great if possible to even unify the two init
functions, but I haven't checked what happens in the middle.
Paolo
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Applied, thanks.
Paolo
- Original Message -
From: Nadav Amit na...@cs.technion.ac.il
To: pbonz...@redhat.com
Cc: kvm@vger.kernel.org, Nadav Amit na...@cs.technion.ac.il
Sent: Sunday, December 7, 2014 10:39:01 AM
Subject: [PATCH kvm-unit-tests] x86: test_conforming_switch misses es
On 10/12/2014 21:23, Marcelo Tosatti wrote:
To test latency between TSC deadline timer
interrupt injection.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm-unit-tests/config/config-x86-common.mak
===
---
On 10/12/2014 21:57, Marcelo Tosatti wrote:
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
This allows achieving low latencies in cyclictest (or any scenario
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Thursday, December 11, 2014 12:59 AM
On 09/12/2014 03:49, Tian, Kevin wrote:
- Now we have XenGT/KVMGT separately maintained, and KVMGT lags
behind XenGT regarding to features and qualities. Likely you'll continue
see stale code
On 11/12/2014 01:33, Tian, Kevin wrote:
My point is that KVMGT doesn't introduce new requirements as what's
required in IGD passthrough case, because all the hacks you see now
is to satisfy guest graphics driver's expectation. I haven't follow up the
KVM IGD passthrough progress, but if it
We already check 'len' above to make sure it already isn't
negative here, so indeed, (addr + len addr) should never be happened.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
---
virt/kvm/coalesced_mmio.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/virt/kvm/coalesced_mmio.c
On Thu, Dec 11, 2014 at 12:37:57AM +0100, Paolo Bonzini wrote:
On 10/12/2014 21:57, Marcelo Tosatti wrote:
For the hrtimer which emulates the tscdeadline timer in the guest,
add an option to advance expiration, and busy spin on VM-entry waiting
for the actual expiration time to elapse.
On Wed, Dec 10, 2014 at 10:49:52PM +0100, Paolo Bonzini wrote:
On 10/12/2014 21:23, Marcelo Tosatti wrote:
To test latency between TSC deadline timer
interrupt injection.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: kvm-unit-tests/config/config-x86-common.mak
Several hypervisors need MSR auto load/restore feature.
We read MSRs from VM-entry MSR load area which specified by L1,
and load them via kvm_set_msr in the nested entry.
When nested exit occurs, we get MSRs via kvm_get_msr, writing
them to L1`s MSR store area. After this, we read MSRs from
This patch improve checks required by Intel Software Developer Manual.
- SMM MSRs are not allowed.
- microcode MSRs are not allowed.
- check x2apic MSRs only when LAPIC is in x2apic mode.
- MSR switch areas must be aligned to 16 bytes.
- address of first and last byte in MSR switch areas
On nested entry:
- check msr switch area.
- load L2's MSRs. If failed, terminate nested entry
and load L1's state. If failed on loading L1's MSRs
again, do nested vmx abort.
On nested exit:
- restore L2's MSRs. If failed, do nested vmx abort.
- load L1's MSRs. If failed, do nested vmx
-Original Message-
From: Alex Williamson [mailto:alex.william...@redhat.com]
Sent: Monday, December 08, 2014 1:21 PM
To: Wu, Feng
Cc: Eric Auger; t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
x...@kernel.org; g...@kernel.org; pbonz...@redhat.com;
dw...@infradead.org;
Dear Sir
Did your website get hit by Google Penguin update on October 17th 2014? What
basically is Google Penguin Update? It is actually a code name for Google
algorithm which aims at decreasing your websites search engine rankings that
violate Googles guidelines by using black hat SEO
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