RE: [PATCH] kvm/vmx: EPTP switching test

On 17/11/2015 18:18, Paolo Bonzini wrote: > On 17/11/2015 02:45, Zhang, Yang Z wrote: > > We have a different version in hand which is using separate EPTP. > > Can you say in advance what you are using EPTP switching for? Offlist if > necessary. Hi Paolo, We are using EPTP switching for a

Re: [PATCH 1/2] arm64: KVM: Fix AArch32 to AArch64 register mapping

Hi Marc, On 16/11/15 10:28, Marc Zyngier wrote: When running a 32bit guest under a 64bit hypervisor, the ARMv8 architecture defines a mapping of the 32bit registers in the 64bit space. This includes banked registers that are being demultiplexed over the 64bit ones. On exception caused by an

Re: [PATCH v5 2/3] target-i386: reorganize TSC rate setting code

On Tue, Nov 17, 2015 at 01:20:38PM +0800, Haozhong Zhang wrote: > Following two changes are made to the TSC rate setting code in > kvm_arch_init_vcpu(): > * The code is moved to a new function kvm_arch_set_tsc_khz(). > * If setting user-specified TSC rate fails and the host TSC rate is >

Re: [PATCH v5 1/3] target-i386: fallback vcpu's TSC rate to value returned by KVM

On 11/17/15 11:14, Eduardo Habkost wrote: > On Tue, Nov 17, 2015 at 01:20:37PM +0800, Haozhong Zhang wrote: > > If no user-specified TSC rate is present, we will try to set > > env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. > > > > Signed-off-by: Haozhong Zhang

Re: [PATCH] kvm/vmx: EPTP switching test

On 17/11/2015 11:44, Wang, Wei W wrote: > On 17/11/2015 18:18, Paolo Bonzini wrote: >> On 17/11/2015 02:45, Zhang, Yang Z wrote: >>> We have a different version in hand which is using separate >>> EPTP. >> >> Can you say in advance what you are using EPTP switching for? >> Offlist if

Re: [PATCH 12/21] arm64: KVM: Implement fpsimd save/restore

On 17/11/15 11:13, Steve Capper wrote: > On 16 November 2015 at 13:11, Marc Zyngier wrote: >> Implement the fpsimd save restore, keeping the lazy part in >> assembler (as returning to C would be overkill). >> >> Signed-off-by: Marc Zyngier >> --- >>

Re: [PATCH 12/21] arm64: KVM: Implement fpsimd save/restore

On 17/11/15 11:49, Steve Capper wrote: > On 17 November 2015 at 11:25, Marc Zyngier wrote: >> On 17/11/15 11:13, Steve Capper wrote: >>> On 16 November 2015 at 13:11, Marc Zyngier wrote: Implement the fpsimd save restore, keeping the lazy part in

Re: [PATCH v5 1/3] target-i386: fallback vcpu's TSC rate to value returned by KVM

On Tue, Nov 17, 2015 at 01:20:37PM +0800, Haozhong Zhang wrote: > If no user-specified TSC rate is present, we will try to set > env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. > > Signed-off-by: Haozhong Zhang > --- > target-i386/kvm.c | 12 > 1

Re: [kvm-unit-tests] x86: pkeys: add test for PKEYS

On 16/11/2015 08:53, Huaitong Han wrote: > Signed-off-by: Huaitong Han > > diff --git a/config/config-x86-common.mak b/config/config-x86-common.mak > index c2f9908..2ef98cc 100644 > --- a/config/config-x86-common.mak > +++ b/config/config-x86-common.mak > @@ -36,7 +36,8

Re: [kvm-unit-tests] x86: smap: add smap check to unittests.cfg

On 16/11/2015 08:53, Huaitong Han wrote: > Signed-off-by: Huaitong Han > > diff --git a/x86/unittests.cfg b/x86/unittests.cfg > index 14e36a4..6d3dc89 100644 > --- a/x86/unittests.cfg > +++ b/x86/unittests.cfg > @@ -72,6 +72,10 @@ groups = vmexit > file = access.flat >

Re: [PATCH v5 3/3] target-i386: add support to migrate vcpu's TSC rate

Hi, On Tue, Nov 17, 2015 at 01:20:39PM +0800, Haozhong Zhang wrote: > This patch enables migrating vcpu's TSC rate. If KVM on the destination > machine supports TSC scaling, guest programs will observe a consistent > TSC rate across the migration. > > If TSC scaling is not supported on the

Re: [PATCH v5 2/3] target-i386: reorganize TSC rate setting code

On 11/17/15 11:32, Eduardo Habkost wrote: > On Tue, Nov 17, 2015 at 01:20:38PM +0800, Haozhong Zhang wrote: > > Following two changes are made to the TSC rate setting code in > > kvm_arch_init_vcpu(): > > * The code is moved to a new function kvm_arch_set_tsc_khz(). > > * If setting

Re: [PATCH v5 3/3] target-i386: add support to migrate vcpu's TSC rate

On 11/17/15 11:40, Eduardo Habkost wrote: > Hi, > > On Tue, Nov 17, 2015 at 01:20:39PM +0800, Haozhong Zhang wrote: > > This patch enables migrating vcpu's TSC rate. If KVM on the destination > > machine supports TSC scaling, guest programs will observe a consistent > > TSC rate across the

Re: [PATCH v5 2/3] target-i386: reorganize TSC rate setting code

On Tue, Nov 17, 2015 at 10:07:53PM +0800, Haozhong Zhang wrote: > On 11/17/15 11:32, Eduardo Habkost wrote: > > On Tue, Nov 17, 2015 at 01:20:38PM +0800, Haozhong Zhang wrote: > > > Following two changes are made to the TSC rate setting code in > > > kvm_arch_init_vcpu(): > > > * The code is

[PATCH v3 3/4] KVM: X86: Implementation of DEBUGCTLMSR is moved

Move the old implementation of DEBUGCTLMSR from x86.c to vmx.c Signed-off-by: Jian Zhou Signed-off-by: Stephen He --- arch/x86/kvm/x86.c | 24 +--- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git

[PATCH v3 4/4] KVM: VMX: Implementation of DEBUGCTLMSR and LBRV

The new implementation of VMX DEBUGCTLMSR is moved to here. Using msr intercept bitmap and arrays(save/restore LBR MSRs) in kvm_vcpu_arch struct to support LBR virtualization, and a parameter of kvm_intel module is added to permanently disable LBRV. Userspace can get/set contents of LBR MSRs, so

[PATCH v3 1/4] KVM: X86: Names and addresses of LBR MSRs

Signed-off-by: Jian Zhou Signed-off-by: Stephen He --- arch/x86/include/asm/msr-index.h | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h

[PATCH v3 0/4] KVM: VMX: enable LBR virtualization

With host CPU model SandyBridge while using guest CPU model core2duo(addresses of MSRs recording last branch information between these two CPUs are different), to read the contents of LBR MSRs in the guest, but the result is not correct, the reason is that these MSRs do not exist in the physical

[PATCH v3 2/4] KVM: X86: Add arrays to save/restore LBR MSRs

Add arrays in kvm_vcpu_arch struct to save/restore host/guest LBR MSRs at vm exit/entry time. Signed-off-by: Jian Zhou Signed-off-by: Stephen He --- arch/x86/include/asm/kvm_host.h | 22 -- 1 file changed, 16

Re: [PATCH v2 3/4] KVM: x86: request interrupt window when IRQ chip is split

On 17/11/2015 00:26, Matt Gingell wrote: > Before this patch, we incorrectly enter the guest without requesting an > interrupt window if the IRQ chip is split between user space and the > kernel. > > Because lapic_in_kernel no longer implies the PIC is in the kernel, this > patch tests

Re: [PATCH V2 1/3] target-i386: add pkeys support for cpuid handling

On 16/11/2015 08:52, Huaitong Han wrote: > This patch adds pkeys support for cpuid handling. > > Signed-off-by: Huaitong Han > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 4d1b085..2ff73ee 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@

Re: [PATCH 2/2] arm64: KVM: Add workaround for Cortex-A57 erratum 834220

Hi Marc, On Mon, Nov 16, 2015 at 10:28:18AM +, Marc Zyngier wrote: > Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults > when a Stage 1 permission fault or device alignment fault should > have been reported. > > This patch implements the workaround (which is to validate

Re: [PATCH 12/21] arm64: KVM: Implement fpsimd save/restore

On 16 November 2015 at 13:11, Marc Zyngier wrote: > Implement the fpsimd save restore, keeping the lazy part in > assembler (as returning to C would be overkill). > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/Makefile | 1 + >

Re: [PATCH 12/21] arm64: KVM: Implement fpsimd save/restore

On 17 November 2015 at 11:25, Marc Zyngier wrote: > On 17/11/15 11:13, Steve Capper wrote: >> On 16 November 2015 at 13:11, Marc Zyngier wrote: >>> Implement the fpsimd save restore, keeping the lazy part in >>> assembler (as returning to C would be

Re: [PATCH 05/10] KVM: x86: MMU: Use for_each_rmap_spte macro instead of pte_list_walk()

On 16/11/2015 03:51, Takuya Yoshikawa wrote: > What kvm_mmu_mark_parents_unsync() does is: > > for each p_i in sp->parent_ptes rmap chain > mark_unsync(p_i); > > Then, mark_unsync() finds the parent sp including that p_i to > set ->unsync_child_bitmap and increment ->unsync_children if >

Re: [PATCH v8 0/5] implement vNVDIMM

Ping... Do you have any comment on this patchset? Could it be applied to somewhere if it is okay for you? Thanks! On 11/16/2015 06:50 PM, Xiao Guangrong wrote: This patchset can be found at: https://github.com/xiaogr/qemu.git nvdimm-v8 It is based on pci branch on Michael's tree and

[PATCH v3 1/3] target-i386: add pkeys support for cpuid handling

This patch adds pkeys support for cpuid handling. Signed-off-by: Huaitong Han diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 4d1b085..3c11e02 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -264,6 +264,17 @@ static const char

[PATCH v3 3/3] target-i386: add pkeys support for vm migration

This patch adds pkeys support for vm migration. Signed-off-by: Huaitong Han diff --git a/target-i386/machine.c b/target-i386/machine.c index a0df64b..1b190c7 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -725,6 +725,26 @@ static const

[PATCH v3 0/3] target-i386: add memory protection-key support

Changes in v3: *Fix cpuid_7_0_ecx_feature_name error. Changes in v2: *Fix memcpy error for xsave state. *Fix TCG_7_0_ECX_FEATURES to 0. *Make subjects more readable. The protection-key feature provides an additional mechanism by which IA-32e paging controls access to usermode addresses.

[PATCH v3 2/3] target-i386: add pkeys support for xsave state handling

This patch adds pkeys support for xsave state handling. Signed-off-by: Huaitong Han diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3c11e02..456cb3b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -487,6 +487,8 @@ static const ExtSaveArea

[kvm-unit-tests v2] x86: pkeys: add test for memory protection-key

Changes in v2: * Move pku.flat from config-x86-common.mak to config-x86_64.mak. The protection-key feature provides an additional mechanism by which IA-32e paging controls access to usermode addresses. The specification of Protection Keys can be found at SDM (4.6.2, volume 3)

Re: [PATCH 02/10] KVM: x86: MMU: Add helper function to clear a bit in unsync child bitmap

On 11/12/2015 07:50 PM, Takuya Yoshikawa wrote: + if (!ret) { + clear_unsync_child_bit(sp, i); + continue; + } else if (ret > 0) { nr_unsync_leaf += ret;

[RFC] kvmtool: add support for modern virtio-pci

This is a first go at adding support for the modern (based on the 1.0 virtio spec) virtio-pci implementation. kvmtool makes it simple to add additional transports such as this because of it's layering, so we are able to add it as a 3rd (after legacy virtio-pci and virtio-mmio) transport layer,

[PATCH v3 1/7] KVM, pkeys: expose CPUID/CR4 to guest

This patch exposes CPUID/CR4 to guest. X86_FEATURE_PKU is referred to as "PKU" in the hardware documentation: CPUID.7.0.ECX[3]:PKU. X86_FEATURE_OSPKE is software support for pkeys, enumerated with CPUID.7.0.ECX[4]:OSPKE, and it reflects the setting of CR4.PKE(bit 22). Signed-off-by: Huaitong Han

[PATCH v3 0/7] KVM, pkeys: add memory protection-key support

Changes in v3: *Add comments for patch that disable PKU feature without ept. Changes in v2: *Add pku.c for kvm-unit-tests. *Optimize permission_fault codes for patch4. *Delete is_long_mode and PK for patch5. *Squash cpuid and cr4 patches. The protection-key feature provides an additional

[PATCH v3 7/7] KVM, pkeys: disable PKU feature without ept

This patch disables CPUID:PKU without ept, becase pkeys is not supported with softmmu. Signed-off-by: Huaitong Han diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ece687b..e422f0a 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -447,6

[PATCH v3 6/7] KVM, pkeys: add pkeys support for xsave state

This patch adds pkeys support for xsave state. Signed-off-by: Huaitong Han diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index f2afa5f..0f71d5d 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -182,7 +182,8 @@ bool

[PATCH v3 3/7] KVM, pkeys: update memeory permission bitmask for pkeys

Pkeys define a new status bit in the PFEC. PFEC.PK (bit 5), if some conditions is true, the fault is considered as a PKU violation. This patch updates memeory permission bitmask for pkeys. Signed-off-by: Huaitong Han diff --git a/arch/x86/include/asm/kvm_host.h

[PATCH v3 4/7] KVM, pkeys: add pkeys support for permission_fault logic

Protection keys define a new 4-bit protection key field (PKEY) in bits 62:59 of leaf entries of the page tables, the PKEY is an index to PKRU register(16 domains), every domain has 2 bits(write disable bit, access disable bit). Static logic has been produced in update_permission_bitmask, dynamic

[PATCH v3 2/7] KVM, pkeys: disable pkeys for guests in non-paging mode

Pkeys is disabled if CPU is in non-paging mode in hardware. However KVM always uses paging mode to emulate guest non-paging, mode with TDP. To emulate this behavior, pkeys needs to be manually disabled when guest switches to non-paging mode. Signed-off-by: Huaitong Han

[PATCH v3 5/7] KVM, pkeys: Add pkeys support for gva_to_gpa funcions

This patch adds pkeys support for gva_to_gpa funcions. Signed-off-by: Huaitong Han diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7a84b83..bd942f3 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3960,6 +3960,7 @@ gpa_t

Re: [PATCH 05/10] KVM: x86: MMU: Use for_each_rmap_spte macro instead of pte_list_walk()

On 11/12/2015 07:52 PM, Takuya Yoshikawa wrote: kvm_mmu_mark_parents_unsync() alone uses pte_list_walk(), witch does nearly the same as the for_each_rmap_spte macro. The only difference is that is_shadow_present_pte() checks cannot be placed there because kvm_mmu_mark_parents_unsync() can be

Re: [PATCH 09/10 RFC] KVM: x86: MMU: Move parent_pte handling from kvm_mmu_get_page() to link_shadow_page()

On 11/12/2015 07:56 PM, Takuya Yoshikawa wrote: Every time kvm_mmu_get_page() is called with a non-NULL parent_pte argument, link_shadow_page() follows that to set the parent entry so that the new mapping will point to the returned page table. Moving parent_pte handling there allows to clean

Re: [PATCH] virtio_ring: Shadow available ring flags & index

On Tue, Nov 17, 2015 at 08:08:18PM -0800, Venkatesh Srinivas wrote: > On Mon, Nov 16, 2015 at 7:46 PM, Xie, Huawei wrote: > > > On 11/14/2015 7:41 AM, Venkatesh Srinivas wrote: > > > On Wed, Nov 11, 2015 at 02:34:33PM +0200, Michael S. Tsirkin wrote: > > >> On Tue, Nov 10,

Re: [PATCH 07/10] KVM: x86: MMU: Encapsulate the type of rmap-chain head in a new struct

On 11/12/2015 07:55 PM, Takuya Yoshikawa wrote: @@ -1720,7 +1724,7 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, * this feature. See the comments in kvm_zap_obsolete_pages(). */ list_add(>link, >kvm->arch.active_mmu_pages); -

Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

On 16/11/2015 20:03, Radim Krčmář wrote: > 2015-11-09 10:46+0800, Feng Wu: >> Use vector-hashing to handle lowest-priority interrupts for >> posted-interrupts. As an example, modern Intel CPUs use this >> method to handle lowest-priority interrupts. > > (I don't think it's a good idea that the

Re: [PATCH] kvm/vmx: EPTP switching test

On 17/11/2015 02:45, Zhang, Yang Z wrote: > We have a different version in hand which is using separate EPTP. Can you say in advance what you are using EPTP switching for? Offlist if necessary. Paolo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to

Re: [PATCH] kvm/vmx: EPTP switching test

On 16/11/2015 19:18, =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= wrote: >> > No idea how would I even test it, so I'm not interested in #VE at this >> > point. If you are - go ahead and post a patch for that on top though, >> > why not. > I thought that it's going to be simpler to provide