RE: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

Hello! > I messed up the "load into xzr" test royally in the last attached patch. > It was quite wrong. Yes, because "mov %0, xzr" is not trapped. > I have now tested > > asm volatile( > "str %3, [%1]\n\t" > "ldr wzr, [%1]\n\t" > "str wzr, [%2]\n\t" > "ldr %0, [%2]\n\t"

Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers

On 07/12/15 14:31, Shannon Zhao wrote: > > > On 2015/12/7 22:06, Marc Zyngier wrote: >> On 03/12/15 06:11, Shannon Zhao wrote: >>> From: Shannon Zhao >>> >>> We are about to trap and emulate acccesses to each PMU register >> >> s/acccesses/accesses/ >> >>> individually.

[PATCH 4.3 034/125] MIPS: KVM: Fix ASID restoration logic

4.3-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 002374f371bd02df864cce1fe85d90dc5b292837 upstream. ASID restoration on guest resume should determine the guest execution mode based on the guest

Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers

On 2015/12/7 22:06, Marc Zyngier wrote: On 03/12/15 06:11, Shannon Zhao wrote: From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register s/acccesses/accesses/ individually. This adds the context offsets for the AArch64 PMU registers and

Re: [PATCH v5 00/21] KVM: ARM64: Add guest PMU support

Hi Marc, On 2015/12/7 22:11, Marc Zyngier wrote: Shannon, On 03/12/15 06:11, Shannon Zhao wrote: From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped

[PATCH 4.1 34/95] MIPS: KVM: Fix CACHE immediate offset sign extension

4.1-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit c5c2a3b998f1ff5a586f9d37e154070b8d550d17 upstream. The immediate field of the CACHE instruction is signed, so ensure that it gets sign extended by

Re: [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device

On 07/12/15 14:37, Shannon Zhao wrote: > > > On 2015/12/7 21:56, Marc Zyngier wrote: >>> +static int kvm_arm_pmu_set_attr(struct kvm_device *dev, + struct kvm_device_attr *attr) +{ + switch (attr->group) { + case KVM_DEV_ARM_PMU_GRP_IRQ: { +

Re: [PATCH v5 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a new case to emulate writing > PMCNTENSET or PMCNTENCLR register. > > When writing to

Re: [PATCH v5 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or > reset_unknown_cp15 for its reset handler. Add access handler which > emulates writing and reading PMXEVTYPER register. When writing to >

Re: [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/7 21:56, Marc Zyngier wrote: +static int kvm_arm_pmu_set_attr(struct kvm_device *dev, >+ struct kvm_device_attr *attr) >+{ >+ switch (attr->group) { >+ case KVM_DEV_ARM_PMU_GRP_IRQ: { >+ int __user *uaddr = (int __user *)(long)attr->addr; >+

Re: [PATCH v5 00/21] KVM: ARM64: Add guest PMU support

On 07/12/15 14:47, Shannon Zhao wrote: > Hi Marc, > > On 2015/12/7 22:11, Marc Zyngier wrote: >> Shannon, >> >> On 03/12/15 06:11, Shannon Zhao wrote: >>> From: Shannon Zhao >>> >>> This patchset adds guest PMU support for KVM on ARM64. It takes >>> trap-and-emulate

[PATCH 4.3 036/125] MIPS: KVM: Uninit VCPU in vcpu_create error path

4.3-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 585bb8f9a5e592f2ce7abbe5ed3112d5438d2754 upstream. If either of the memory allocations in kvm_arch_vcpu_create() fail, the vcpu which has been

[PATCH 4.3 035/125] MIPS: KVM: Fix CACHE immediate offset sign extension

4.3-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit c5c2a3b998f1ff5a586f9d37e154070b8d550d17 upstream. The immediate field of the CACHE instruction is signed, so ensure that it gets sign extended by

Re: [RFC PATCH V2 0/3] IXGBE/VFIO: Add live migration support for SRIOV NIC

On 12/5/2015 1:07 AM, Alexander Duyck wrote: We still need to support Windows guest for migration and this is why our patches keep all changes in the driver since it's impossible to change Windows kernel. That is a poor argument. I highly doubt Microsoft is interested in having to modify all

Re: [PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > Here we plan to support virtual PMU for guest by full software > emulation, so define some basic structs and functions preparing for > futher steps. Define struct kvm_pmc for performance monitor counter and

Re: [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement > the kvm_device_ops for it. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v5 00/21] KVM: ARM64: Add guest PMU support

Shannon, On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > This patchset adds guest PMU support for KVM on ARM64. It takes > trap-and-emulate approach. When guest wants to monitor one event, it > will be trapped by KVM and KVM will call perf_event API to

Re: [PATCH v5 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > Add reset handler which gets host value of PMCR_EL0 and make writable > bits architecturally UNKNOWN except PMCR.E to zero. Add a common access > handler for PMU registers which emulates writing and reading

Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers

On 03/12/15 06:11, Shannon Zhao wrote: > From: Shannon Zhao > > We are about to trap and emulate acccesses to each PMU register s/acccesses/accesses/ > individually. This adds the context offsets for the AArch64 PMU > registers and their AArch32 counterparts. > >

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

Hi Mario, On 07/12/15 16:40, Mario Smarduch wrote: > Hi Marc, > > On 12/7/2015 2:53 AM, Marc Zyngier wrote: >> Implement the vgic-v3 save restore as a direct translation of >> the assembly code version. >> >> Signed-off-by: Marc Zyngier >> --- >>

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On 07/12/15 17:18, Mario Smarduch wrote: > > > On 12/7/2015 8:52 AM, Marc Zyngier wrote: >> Hi Mario, >> >> On 07/12/15 16:40, Mario Smarduch wrote: >>> Hi Marc, >>> >>> On 12/7/2015 2:53 AM, Marc Zyngier wrote: Implement the vgic-v3 save restore as a direct translation of the assembly

Re: [PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu

On 07/12/15 15:05, Marc Zyngier wrote: > On 03/12/15 06:11, Shannon Zhao wrote: >> From: Shannon Zhao >> >> Here we plan to support virtual PMU for guest by full software >> emulation, so define some basic structs and functions preparing for >> futher steps. Define struct

live migration vs device assignment (was Re: [RFC PATCH V2 00/10] Qemu: Add live migration support for SRIOV NIC)

On Tue, Nov 24, 2015 at 09:35:17PM +0800, Lan Tianyu wrote: > This patchset is to propose a solution of adding live migration > support for SRIOV NIC. I thought about what this is doing at the high level, and I do have some value in what you are trying to do, but I also think we need to clarify

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On 12/7/2015 8:52 AM, Marc Zyngier wrote: > Hi Mario, > > On 07/12/15 16:40, Mario Smarduch wrote: >> Hi Marc, >> >> On 12/7/2015 2:53 AM, Marc Zyngier wrote: >>> Implement the vgic-v3 save restore as a direct translation of >>> the assembly code version. >>> >>> Signed-off-by: Marc Zyngier

[PATCH 4.2 045/124] MIPS: KVM: Fix CACHE immediate offset sign extension

4.2-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit c5c2a3b998f1ff5a586f9d37e154070b8d550d17 upstream. The immediate field of the CACHE instruction is signed, so ensure that it gets sign extended by

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

Hi Marc, On 12/7/2015 2:53 AM, Marc Zyngier wrote: > Implement the vgic-v3 save restore as a direct translation of > the assembly code version. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/Makefile | 1 + > arch/arm64/kvm/hyp/hyp.h| 3 + >

Re: [RFC PATCH V2 0/3] IXGBE/VFIO: Add live migration support for SRIOV NIC

On Mon, Dec 07, 2015 at 09:12:08AM -0800, Alexander Duyck wrote: > On Mon, Dec 7, 2015 at 7:40 AM, Lan, Tianyu wrote: > > On 12/5/2015 1:07 AM, Alexander Duyck wrote: > >>> > >>> > >>> We still need to support Windows guest for migration and this is why our > >>> patches

[PATCH 4.2 044/124] MIPS: KVM: Fix ASID restoration logic

4.2-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 002374f371bd02df864cce1fe85d90dc5b292837 upstream. ASID restoration on guest resume should determine the guest execution mode based on the guest

[PATCH 4.1 33/95] MIPS: KVM: Fix ASID restoration logic

4.1-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 002374f371bd02df864cce1fe85d90dc5b292837 upstream. ASID restoration on guest resume should determine the guest execution mode based on the guest

[PATCH 4.2 046/124] MIPS: KVM: Uninit VCPU in vcpu_create error path

4.2-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 585bb8f9a5e592f2ce7abbe5ed3112d5438d2754 upstream. If either of the memory allocations in kvm_arch_vcpu_create() fail, the vcpu which has been

[PATCH 4.1 35/95] MIPS: KVM: Uninit VCPU in vcpu_create error path

4.1-stable review patch. If anyone has any objections, please let me know. -- From: James Hogan commit 585bb8f9a5e592f2ce7abbe5ed3112d5438d2754 upstream. If either of the memory allocations in kvm_arch_vcpu_create() fail, the vcpu which has been

Re: [PATCH v3 01/22] arm64: Add macros to read/write system registers

On Mon, Dec 07, 2015 at 10:53:17AM +, Marc Zyngier wrote: > From: Mark Rutland > > Rather than crafting custom macros for reading/writing each system > register provide generics accessors, read_sysreg and write_sysreg, for > this purpose. > > Unlike read_cpuid, calls

Re: [PATCH v3 01/22] arm64: Add macros to read/write system registers

On Mon, Dec 07, 2015 at 05:35:20PM +, Catalin Marinas wrote: > On Mon, Dec 07, 2015 at 10:53:17AM +, Marc Zyngier wrote: > > From: Mark Rutland > > > > Rather than crafting custom macros for reading/writing each system > > register provide generics accessors,

Re: [RFC PATCH V2 0/3] IXGBE/VFIO: Add live migration support for SRIOV NIC

On Mon, Dec 7, 2015 at 7:40 AM, Lan, Tianyu wrote: > On 12/5/2015 1:07 AM, Alexander Duyck wrote: >>> >>> >>> We still need to support Windows guest for migration and this is why our >>> patches keep all changes in the driver since it's impossible to change >>> Windows

RE: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

Hello! > But, if Pavel doesn't > mind trying them out on his system, then it'd be good to know if they > reproduce there. I'd like to find out if it's a test case problem or > something else strange going on with environments. Does not build, applied to master: --- cut ---

RE: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

Hello! > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > issue didn't reproduce for me. It's quite possible my test cases are > flawed, so I'm not making any claims about the validity of the series This is indeed very interesting, so i'll take a look at it. For now

RE: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

Hello! > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > issue didn't reproduce for me. It's quite possible my test cases are > flawed Indeed they are, a very little thing fell through again... :) It's not just SP, it's SP_EL0. And you never initialize it to anything

Re: powerpc/64: Include KVM guest test in all interrupt vectors

On Thu, 2015-12-11 at 05:44:42 UTC, Paul Mackerras wrote: > Currently, if HV KVM is configured but PR KVM isn't, we don't include > a test to see whether we were interrupted in KVM guest context for the > set of interrupts which get delivered directly to the guest by hardware > if they occur in

[PATCH v3 06/22] arm64: KVM: Implement timer save/restore

Implement the timer save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/hyp.h | 3 ++ arch/arm64/kvm/hyp/timer-sr.c| 72

[PATCH v3 09/22] arm64: KVM: Implement debug save/restore

Implement the debug save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Christoffer Dall

[PATCH v3 03/22] arm64: KVM: Implement vgic-v2 save/restore

Implement the vgic-v2 save restore (mostly) as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/hyp/Makefile | 5 +++ arch/arm64/kvm/hyp/hyp.h| 3 ++

[PATCH v3 04/22] KVM: arm/arm64: vgic-v3: Make the LR indexing macro public

We store GICv3 LRs in reverse order so that the CPU can save/restore them in rever order as well (don't ask why, the design is crazy), and yet generate memory traffic that doesn't completely suck. We need this macro to be available to the C version of save/restore. Signed-off-by: Marc Zyngier

[PATCH v3 01/22] arm64: Add macros to read/write system registers

From: Mark Rutland Rather than crafting custom macros for reading/writing each system register provide generics accessors, read_sysreg and write_sysreg, for this purpose. Unlike read_cpuid, calls to read_exception_reg are never expected to be optimized away or replaced

[PATCH v3 16/22] arm64: KVM: Add panic handling

Add the panic handler, together with the small bits of assembly code to call the kernel's panic implementation. Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/hyp-entry.S | 11 ++-

[PATCH v3 00/22] arm64: KVM: Rewriting the world switch in C

Once upon a time, the KVM/arm64 world switch was a nice, clean, lean and mean piece of hand-crafted assembly code. Over time, features have crept in, the code has become harder to maintain, and the smallest change is a pain to introduce. The VHE patches are a prime example of why this doesn't work

[PATCH v3 02/22] arm64: KVM: Add a HYP-specific header file

In order to expose the various EL2 services that are private to the hypervisor, add a new hyp.h file. So far, it only contains mundane things such as section annotation and VA manipulation. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/hyp.h | 33

[PATCH v3 20/22] arm64: KVM: Turn system register numbers to an enum

Having the system register numbers as #defines has been a pain since day one, as the ordering is pretty fragile, and moving things around leads to renumbering and epic conflict resolutions. Now that we're mostly acessing the sysreg file in C, an enum is a much better type to use, and we can clean

[PATCH v3 10/22] arm64: KVM: Implement guest entry

Contrary to the previous patch, the guest entry is fairly different from its assembly counterpart, mostly because it is only concerned with saving/restoring the GP registers, and nothing else. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 +

[PATCH v3 21/22] arm64: KVM: Cleanup asm-offset.c

As we've now rewritten most of our code-base in C, most of the KVM-specific code in asm-offset.c is useless. Delete-time again! Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall --- arch/arm64/kernel/asm-offsets.c | 39

[PATCH v3 14/22] arm64: KVM: Implement TLB handling

Implement the TLB handling as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/entry.S | 1 + arch/arm64/kvm/hyp/tlb.c

[PATCH v3 22/22] arm64: KVM: Remove weak attributes

As we've now switched to the new world switch implementation, remove the weak attributes, as nobody is supposed to override it anymore. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/debug-sr.c | 5 ++--- arch/arm64/kvm/hyp/hyp-entry.S | 3 ---

[PATCH v3 08/22] arm64: KVM: Implement 32bit system register save/restore

Implement the 32bit system register save/restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/hyp.h | 2 ++ arch/arm64/kvm/hyp/sysreg-sr.c | 47

[PATCH v3 19/22] arm64: KVM: Move away from the assembly version of the world switch

This is it. We remove all of the code that has now been rewritten. Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall --- arch/arm64/kvm/Makefile |2 - arch/arm64/kvm/hyp.S| 1081

[PATCH v3 15/22] arm64: KVM: HYP mode entry points

Add the entry points for HYP mode (both for hypercalls and exception handling). Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp-entry.S | 203

[PATCH v3 13/22] arm64: KVM: Implement fpsimd save/restore

Implement the fpsimd save restore, keeping the lazy part in assembler (as returning to C would be overkill). Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/entry.S |

[PATCH v3 11/22] arm64: KVM: Add patchable function selector

KVM so far relies on code patching, and is likely to use it more in the future. The main issue is that our alternative system works at the instruction level, while we'd like to have alternatives at the function level. In order to cope with this, add the "hyp_alternate_select" macro that outputs a

[PATCH v3 12/22] arm64: KVM: Implement the core world switch

Implement the core of the world switch in C. Not everything is there yet, and there is nothing to re-enter the world switch either. But this already outlines the code structure well enough. Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall

[PATCH v3 17/22] arm64: KVM: Add compatibility aliases

So far, we've implemented the new world switch with a completely different namespace, so that we could have both implementation compiled in. Let's take things one step further by adding weak aliases that have the same names as the original implementation. The weak attributes allows the new

[PATCH v3 18/22] arm64: KVM: Map the kernel RO section into HYP

In order to run C code in HYP, we must make sure that the kernel's RO section is mapped into HYP (otherwise things break badly). Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall --- arch/arm/kvm/arm.c | 7 +++ 1 file changed, 7

[PATCH v3 07/22] arm64: KVM: Implement system register save/restore

Implement the system register save/restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp.h | 3 ++

[PATCH v7 2/6] KVM: arm/arm64: Move endianness conversion out of vgic_attr_regs_access()

mmio_data_read() and mmio_data_write(), originally used in this function, are limited only to 32 bits. We are going to refactor this code and eventually let it do 64-bit I/O for vGICv3. Therefore, our first step is to get rid of this limitation. We open up these inlines, which consist of

[PATCH v7 5/6] KVM: arm64: Introduce find_reg_by_id()

In order to implement vGICv3 CPU interface access, we will need to perform table lookup of system registers. We would need both index_to_params() and find_reg() exported for that purpose, but instead we export a single function which combines them both. Signed-off-by: Pavel Fedin

[PATCH v7 3/6] KVM: arm/arm64: Refactor vGIC attributes handling code

Separate all implementation-independent code in vgic_attr_regs_access() and move it to vgic.c. This will allow to reuse this code for vGICv3 implementation. vcpu lookup is left where it originally was, because vGICv3 API will expect affinity ID instead of vCPU index, therefore it will be done

[PATCH v7 1/6] KVM: arm/arm64: Add VGICv3 save/restore API documentation

From: Christoffer Dall Factor out the GICv3-specific documentation into a separate documentation file. Add description for how to access distributor, redistributor, and CPU interface registers for GICv3 in this new file. Acked-by: Peter Maydell

[PATCH v7 6/6] KVM: arm64: Implement vGICv3 CPU interface access

Access size is always 64 bits. Since CPU interface state actually affects only a single vCPU, no vGIC locking is done in order to avoid code duplication. Just made sure that the vCPU is not running. Signed-off-by: Pavel Fedin --- arch/arm64/include/uapi/asm/kvm.h | 14 ++-

[PATCH v7 4/6] KVM: arm64: Implement vGICv3 distributor and redistributor access from userspace

The access is done similar to vGICv2, using KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls. Access size for vGICv3 is 64 bits, vgic_attr_regs_access() fixed to support this. The trick with vgic_v3_get_reg_size() is

[PATCH v7 0/6] KVM: arm64: Implement API for vGICv3 live migration

This patchset adds necessary userspace API in order to support vGICv3 live migration. GICv3 registers are accessed using device attribute ioctls, similar to GICv2. v6 => v7: - Rebased on top of linux-next of 07.12.2015, thrown away unnecessary part v5 => v6: - Rebased on top of linux-next of

Re: [PATCH] KVM: PPC: Fix emulation of H_SET_DABR/X on POWER8

On 20/11/15 09:11, Thomas Huth wrote: > In the old DABR register, the BT (Breakpoint Translation) bit > is bit number 61. In the new DAWRX register, the WT (Watchpoint > Translation) bit is bit number 59. So to move the DABR-BT bit > into the position of the DAWRX-WT bit, it has to be shifted by >

Re: [PATCH] KVM: PPC: Fix emulation of H_SET_DABR/X on POWER8

On 20/11/15 09:11, Thomas Huth wrote: > In the old DABR register, the BT (Breakpoint Translation) bit > is bit number 61. In the new DAWRX register, the WT (Watchpoint > Translation) bit is bit number 59. So to move the DABR-BT bit > into the position of the DAWRX-WT bit, it has to be shifted by >

Re: [PATCH v3 01/22] arm64: Add macros to read/write system registers

On 07/12/15 17:45, Mark Rutland wrote: > On Mon, Dec 07, 2015 at 05:35:20PM +, Catalin Marinas wrote: >> On Mon, Dec 07, 2015 at 10:53:17AM +, Marc Zyngier wrote: >>> From: Mark Rutland >>> >>> Rather than crafting custom macros for reading/writing each system >>>

Re: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On Mon, Dec 07, 2015 at 04:36:31PM -0600, Andrew Jones wrote: > On Mon, Dec 07, 2015 at 11:36:28AM +0300, Pavel Fedin wrote: > > Hello! > > > > > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > > > issue didn't reproduce for me. It's quite possible my test cases are > >

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On 12/7/2015 10:20 AM, Marc Zyngier wrote: > On 07/12/15 18:05, Mario Smarduch wrote: >> >> >> On 12/7/2015 9:37 AM, Marc Zyngier wrote: [...] >>> >> >> I was thinking something like 'current_lr[VGIC_V3_LR_INDEX(...)]'. > > That doesn't change anything, the compiler is perfectly able to >

Re: [PATCH v3 06/22] arm64: KVM: Implement timer save/restore

On 12/7/2015 2:53 AM, Marc Zyngier wrote: > Implement the timer save restore as a direct translation of > the assembly code version. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/Makefile | 1 + > arch/arm64/kvm/hyp/hyp.h | 3 ++ >

Re: [PATCH kernel 3/9] KVM: PPC: Rework H_PUT_TCE/H_GET_TCE handlers

On Tue, Sep 15, 2015 at 08:49:33PM +1000, Alexey Kardashevskiy wrote: > This reworks the existing H_PUT_TCE/H_GET_TCE handlers to have one > exit path. This allows next patch to add locks nicely. I don't see a problem with the actual code, but it doesn't seem to match this description: I still

Re: [PATCH kernel 1/9] rcu: Define notrace version of list_for_each_entry_rcu

On Tue, Sep 15, 2015 at 08:49:31PM +1000, Alexey Kardashevskiy wrote: > This defines list_for_each_entry_rcu_notrace and list_entry_rcu_notrace > which use rcu_dereference_raw_notrace instead of rcu_dereference_raw. > This allows using list_for_each_entry_rcu_notrace in real mode (MMU is off). >

Re: [PATCH kernel 1/9] rcu: Define notrace version of list_for_each_entry_rcu

On Tue, Sep 15, 2015 at 08:49:31PM +1000, Alexey Kardashevskiy wrote: > This defines list_for_each_entry_rcu_notrace and list_entry_rcu_notrace > which use rcu_dereference_raw_notrace instead of rcu_dereference_raw. > This allows using list_for_each_entry_rcu_notrace in real mode (MMU is off). >

Re: [PATCH kernel 3/9] KVM: PPC: Rework H_PUT_TCE/H_GET_TCE handlers

On Tue, Sep 15, 2015 at 08:49:33PM +1000, Alexey Kardashevskiy wrote: > This reworks the existing H_PUT_TCE/H_GET_TCE handlers to have one > exit path. This allows next patch to add locks nicely. I don't see a problem with the actual code, but it doesn't seem to match this description: I still

Re: [PATCH kernel 4/9] KVM: PPC: Use RCU for arch.spapr_tce_tables

On Tue, Sep 15, 2015 at 08:49:34PM +1000, Alexey Kardashevskiy wrote: > At the moment spapr_tce_tables is not protected against races. This makes > use of RCU-variants of list helpers. As some bits are executed in real > mode, this makes use of just introduced list_for_each_entry_rcu_notrace(). >

Re: [PATCH kernel 2/9] KVM: PPC: Make real_vmalloc_addr() public

On Tue, Sep 15, 2015 at 08:49:32PM +1000, Alexey Kardashevskiy wrote: > This helper translates vmalloc'd addresses to linear addresses. > It is only used by the KVM MMU code now and resides in the HV KVM code. > We will need it further in the TCE code and the DMA memory preregistration > code

Re: [PATCH kernel 4/9] KVM: PPC: Use RCU for arch.spapr_tce_tables

On Tue, Sep 15, 2015 at 08:49:34PM +1000, Alexey Kardashevskiy wrote: > At the moment spapr_tce_tables is not protected against races. This makes > use of RCU-variants of list helpers. As some bits are executed in real > mode, this makes use of just introduced list_for_each_entry_rcu_notrace(). >

Re: [PATCH kernel 2/9] KVM: PPC: Make real_vmalloc_addr() public

On Tue, Sep 15, 2015 at 08:49:32PM +1000, Alexey Kardashevskiy wrote: > This helper translates vmalloc'd addresses to linear addresses. > It is only used by the KVM MMU code now and resides in the HV KVM code. > We will need it further in the TCE code and the DMA memory preregistration > code

[PATCH kvm-unit-tests] x86: always inline functions called after set_exception_return

set_exception_return forces exceptions handlers to return to a specific address instead of returning to the instruction address pushed by the CPU at the time of the exception. The unit tests apic.c and vmx.c use this functionality to recover from expected exceptions. When using

Re: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On Mon, Dec 07, 2015 at 11:47:44AM +0300, Pavel Fedin wrote: > Hello! > > > But, if Pavel doesn't > > mind trying them out on his system, then it'd be good to know if they > > reproduce there. I'd like to find out if it's a test case problem or > > something else strange going on with

Re: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On Mon, Dec 07, 2015 at 12:48:12PM +0300, Pavel Fedin wrote: > Hello! > > > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > > issue didn't reproduce for me. It's quite possible my test cases are > > flawed > > Indeed they are, a very little thing fell through again...

Re: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On Mon, Dec 07, 2015 at 03:58:11PM -0600, Andrew Jones wrote: > On Mon, Dec 07, 2015 at 12:48:12PM +0300, Pavel Fedin wrote: > > Hello! > > > > > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > > > issue didn't reproduce for me. It's quite possible my test cases are > >

Re: [PATCH v4 0/4] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On Mon, Dec 07, 2015 at 11:36:28AM +0300, Pavel Fedin wrote: > Hello! > > > FYI, I tried writing test cases for this issue with kvm-unit-tests. The > > issue didn't reproduce for me. It's quite possible my test cases are > > flawed, so I'm not making any claims about the validity of the series >

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On 12/7/2015 9:37 AM, Marc Zyngier wrote: > On 07/12/15 17:18, Mario Smarduch wrote: >> >> >> On 12/7/2015 8:52 AM, Marc Zyngier wrote: >>> Hi Mario, >>> >>> On 07/12/15 16:40, Mario Smarduch wrote: Hi Marc, On 12/7/2015 2:53 AM, Marc Zyngier wrote: > Implement the vgic-v3

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On 07/12/15 18:05, Mario Smarduch wrote: > > > On 12/7/2015 9:37 AM, Marc Zyngier wrote: >> On 07/12/15 17:18, Mario Smarduch wrote: >>> >>> >>> On 12/7/2015 8:52 AM, Marc Zyngier wrote: Hi Mario, On 07/12/15 16:40, Mario Smarduch wrote: > Hi Marc, > > On 12/7/2015

Re: [RFC PATCH V2 0/3] IXGBE/VFIO: Add live migration support for SRIOV NIC

On Mon, Dec 7, 2015 at 9:39 AM, Michael S. Tsirkin wrote: > On Mon, Dec 07, 2015 at 09:12:08AM -0800, Alexander Duyck wrote: >> On Mon, Dec 7, 2015 at 7:40 AM, Lan, Tianyu wrote: >> > On 12/5/2015 1:07 AM, Alexander Duyck wrote: >> > If can't do that, we