On 08/10/13 12:26, Raghavendra KT wrote:
On Mon, Oct 7, 2013 at 9:10 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On an (even slightly) oversubscribed system, spinlocks are quickly
becoming a bottleneck, as some vcpus are spinning, waiting for a
lock to be released, while the vcpu holding
On 08/10/13 16:02, Raghavendra K T wrote:
[...]
+ kvm_vcpu_on_spin(vcpu);
Could you also enable CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT for arm and
check if ple handler logic helps further?
we would ideally get one more optimization folded into ple handler if
you enable that.
On 08/10/13 16:13, Raghavendra K T wrote:
On 10/08/2013 08:36 PM, Marc Zyngier wrote:
Just gave it a go, and the results are slightly (but consistently)
worse. Over 10 runs:
Without RELAX_INTERCEPT: Average run 3.3623s
With RELAX_INTERCEPT: Average run 3.4226s
Not massive, but still
+++--
arch/arm64/include/asm/kvm_mmu.h | 12 +-
arch/arm64/include/asm/pgtable-hwdef.h | 2 +
5 files changed, 212 insertions(+), 44 deletions(-)
Looks good to me. For the series:
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
--
Jazz is not dead. It just smells funny
8xA15 guest w/ patch: 6.887s
So we go from a 40x degradation to 1.5x in the 2x overcommit case,
which is vaguely more acceptable.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/kvm_arm.h | 4 +++-
arch/arm/kvm/Kconfig | 1 +
arch/arm/kvm/handle_exit.c | 6
configuration
Marc Zyngier (2):
ARM: KVM: Yield CPU when vcpu executes a WFE
arm64: KVM: Yield CPU when vcpu executes a WFE
arch/arm/include/asm/kvm_arm.h | 4 +++-
arch/arm/kvm/Kconfig | 1 +
arch/arm/kvm/handle_exit.c | 6 +-
arch/arm64/include/asm/kvm_arm.h | 8
. This ensures that other vpus will get a scheduling
boost, allowing the lock to be released more quickly. Also, using
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT slightly improves the performance
when the VM is severely overcommited.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm
On 09/10/13 14:26, Gleb Natapov wrote:
On Wed, Oct 09, 2013 at 03:09:54PM +0200, Alexander Graf wrote:
On 07.10.2013, at 18:53, Gleb Natapov g...@redhat.com wrote:
On Mon, Oct 07, 2013 at 06:30:04PM +0200, Alexander Graf wrote:
On 07.10.2013, at 18:16, Marc Zyngier marc.zyng...@arm.com
On 09/10/13 15:50, Anup Patel wrote:
On Wed, Oct 9, 2013 at 7:48 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/10/13 14:26, Gleb Natapov wrote:
On Wed, Oct 09, 2013 at 03:09:54PM +0200, Alexander Graf wrote:
On 07.10.2013, at 18:53, Gleb Natapov g...@redhat.com wrote:
On Mon, Oct 07
On 09/10/13 16:10, Anup Patel wrote:
On Wed, Oct 9, 2013 at 8:29 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/10/13 15:50, Anup Patel wrote:
On Wed, Oct 9, 2013 at 7:48 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/10/13 14:26, Gleb Natapov wrote:
On Wed, Oct 09, 2013 at 03:09:54PM
.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/kvm_emulate.h | 41
arch/arm/kvm/mmio.c | 74 ++--
arch/arm64/include/asm/kvm_emulate.h | 48 +++
3 files changed, 152 insertions(+), 11
separately.
A branch containing all the relevant changes is at:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
kvm-arm64/be-on-le-3.12-rc4
Cc: Rusty Russell ru...@rustcorp.com.au
Cc: Michael S. Tsirkin m...@redhat.com
Cc: Pawel Moll pawel.m...@arm.com
Marc Zyngier (3):
virtio
: Michael S. Tsirkin m...@redhat.com
Cc: Pawel Moll pawel.m...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/virtio/virtio_mmio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index 1ba0d68
/be-on-le-3.12-rc4
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Marc Zyngier (7):
kvmtool: virt_queue configuration based on endianness
kvmtool: virt_queue: handle guest endianness
kvmtool: convert console backend to support bi-endianness
kvmtool: convert 9p backend
Define a simple infrastructure to configure a virt_queue
depending on the guest endianness, as reported by the feature
flags. At this stage, the endianness is always the host's.
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng
and transports are updated to use the modified API. Only
virtio_mmio is actually changed to do something different.
Cc: Rusty Russell ru...@rustcorp.com.au
Cc: Michael S. Tsirkin m...@redhat.com
Cc: Pawel Moll pawel.m...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/block
...@rustcorp.com.au
Cc: Michael S. Tsirkin m...@redhat.com
Cc: Pawel Moll pawel.m...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/virtio/virtio_ring.c | 8
include/uapi/linux/virtio_ring.h | 8
2 files changed, 16 insertions(+)
diff --git a/drivers/virtio
Advertise bi-endianness support in the feature flags, and provide
byte-swapping of the config structure depending on the guest selection.
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/virtio/net.c | 17
Advertise bi-endianness support in the feature flags, and provide
byte-swapping of the config structure depending on the guest selection.
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/virtio/console.c | 12
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/arm/include/arm-common/kvm-arch.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/kvm/arm/include/arm-common/kvm-arch.h
b/tools/kvm/arm/include/arm
-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/include/kvm/virtio.h | 189 -
tools/kvm/virtio/core.c| 59 +++--
2 files changed, 219 insertions(+), 29 deletions(-)
diff --git a/tools/kvm/include/kvm/virtio.h b/tools/kvm/include/kvm
Advertise bi-endianness support in the feature flags, and provide
byte-swapping of the config structure depending on the guest selection.
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/virtio/blk.c | 34
Advertise bi-endianness support in the feature flags, and provide
byte-swapping of the config structure depending on the guest selection.
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/virtio/9p.c | 5
Hi Michael,
On 12/10/13 19:28, Michael S. Tsirkin wrote:
On Fri, Oct 11, 2013 at 03:36:08PM +0100, Marc Zyngier wrote:
This small patch series adds just enough kernel infrastructure and
fixes to allow a BE guest to use virtio-mmio on a LE host, provided
that the host actually supports
On 14/10/13 09:21, Rusty Russell wrote:
Marc Zyngier marc.zyng...@arm.com writes:
This small patch series adds just enough kernel infrastructure and
fixes to allow a BE guest to use virtio-mmio on a LE host, provided
that the host actually supports such madness.
This has been tested on arm64
On 14/10/13 14:05, Paolo Bonzini wrote:
Il 11/10/2013 16:36, Marc Zyngier ha scritto:
Cc: Pekka Enberg penb...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/arm/include/arm-common/kvm-arch.h | 2 ++
1 file changed, 2
On 14/10/13 14:10, Alexander Graf wrote:
On 14.10.2013, at 15:03, Paolo Bonzini pbonz...@redhat.com wrote:
Il 11/10/2013 16:36, Marc Zyngier ha scritto:
This small patch series adds just enough kernel infrastructure and
fixes to allow a BE guest to use virtio-mmio on a LE host, provided
On 14/10/13 14:39, Alexander Graf wrote:
On 14.10.2013, at 15:24, Marc Zyngier marc.zyng...@arm.com wrote:
On 14/10/13 14:10, Alexander Graf wrote:
On 14.10.2013, at 15:03, Paolo Bonzini pbonz...@redhat.com wrote:
Il 11/10/2013 16:36, Marc Zyngier ha scritto:
This small patch series
On 14/10/13 15:05, Michael S. Tsirkin wrote:
On Mon, Oct 14, 2013 at 02:49:10PM +0100, Marc Zyngier wrote:
On 14/10/13 14:39, Alexander Graf wrote:
On 14.10.2013, at 15:24, Marc Zyngier marc.zyng...@arm.com wrote:
On 14/10/13 14:10, Alexander Graf wrote:
On 14.10.2013, at 15:03, Paolo
On 14/10/13 15:16, Alexander Graf wrote:
On 14.10.2013, at 16:13, Marc Zyngier marc.zyng...@arm.com wrote:
On 14/10/13 15:05, Michael S. Tsirkin wrote:
On Mon, Oct 14, 2013 at 02:49:10PM +0100, Marc Zyngier wrote:
On 14/10/13 14:39, Alexander Graf wrote:
On 14.10.2013, at 15:24, Marc
On 14/10/13 15:56, Paolo Bonzini wrote:
Il 14/10/2013 16:52, Marc Zyngier ha scritto:
Sure. And I imagine this traps back into the kernel to read some
register and find out what the endianness of the accessing CPU is?
Not yet. To be exact, it does the below today. But all virtio device
On 14/10/13 16:22, Paolo Bonzini wrote:
Il 14/10/2013 17:12, Marc Zyngier ha scritto:
On 14/10/13 15:56, Paolo Bonzini wrote:
Il 14/10/2013 16:52, Marc Zyngier ha scritto:
Sure. And I imagine this traps back into the kernel to read some
register and find out what the endianness
On 15/10/13 07:38, Michael S. Tsirkin wrote:
On Tue, Oct 15, 2013 at 09:53:17AM +1030, Rusty Russell wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Mon, Oct 14, 2013 at 06:50:48PM +0200, Paolo Bonzini wrote:
Il 14/10/2013 17:36, Marc Zyngier ha scritto:
Devices are fine in QEMU, it's
On 2013-10-16 02:14, Christoffer Dall wrote:
On Tue, Oct 08, 2013 at 06:38:13PM +0100, Marc Zyngier wrote:
On an (even slightly) oversubscribed system, spinlocks are quickly
becoming a bottleneck, as some vcpus are spinning, waiting for a
lock to be released, while the vcpu holding the lock may
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
tools/kvm/arm/aarch32/include/kvm/kvm-cpu-arch.h | 4
tools/kvm/arm/aarch32/kvm-cpu.c | 26 ++
tools/kvm/arm/aarch64/include/kvm/kvm-cpu-arch.h | 4
tools/kvm/arm/aarch64/kvm-cpu.c
Hi Christoffer,
On 2013-10-22 10:08, Christoffer Dall wrote:
Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses
in
a more generic API than the ARM-specific
On 2013-10-22 10:08, Christoffer Dall wrote:
Support setting the distributor and cpu interface base addresses in
the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition to the ARM specific API.
This has the added benefit of being able to share more code in user
On 2013-10-22 10:08, Christoffer Dall wrote:
Add infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding
the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS
groups
and defining the semantics of the
On 2013-10-22 10:08, Christoffer Dall wrote:
Handle MMIO accesses to the two registers which should support both
the
case where the VMs want to read/write either of these registers and
the
case where user space reads/writes these registers to do save/restore
of
the VGIC state.
Note that the
. This ensures that other vpus will get a scheduling
boost, allowing the lock to be released more quickly. Also, using
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT slightly improves the performance
when the VM is severely overcommited.
Acked-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier
When booting a vcpu using PSCI, make sure we start it with the
endianness of the caller. Otherwise, secondaries can be pretty
unhappy to execute a BE kernel in LE mode...
This conforms to PSCI spec Rev B, 5.13.3.
Acked-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier
host
- A performance improvement for overcommitted VMs (same as the equivalent
patch for ARM)
Marc Zyngier (3):
arm64: KVM: Yield CPU when vcpu executes a WFE
arm/arm64: KVM: MMIO support for BE guest
arm/arm64: KVM: PSCI
-by: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/kvm_emulate.h | 41 +
arch/arm/kvm/mmio.c | 86 +++-
arch/arm64/include/asm/kvm_emulate.h | 48
Paolo,
On 11/11/13 17:56, Paolo Bonzini wrote:
Il 11/11/2013 16:49, Christoffer Dall ha scritto:
I don't think it would have made much sense - that patch was part of a
series that was touching mainly arch/arm/kvm/* and therefore I
included it in my pull. It would have been strange to have a
On 12/11/13 09:41, Andrew Jones wrote:
On Mon, Nov 11, 2013 at 07:41:30PM +0100, Paolo Bonzini wrote:
Il 11/11/2013 19:26, Marc Zyngier ha scritto:
The pull requests were clean and my life wasn't complicated much... On
the other hand I'm trying to understand if there's something that can
issue where we were storing the
physical address as a 32 bit unsigned long (on arm), truncating the
physical address for addresses above the 4GB limit. This caused
breakage on Keystone.
Reported-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Signed-off
comments on the exported
functions making it a bit easier to understand the init flow by only
looking at vgic.c.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Looks good to me:
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
---
arch/arm/kvm/arm.c |7 ---
virt/kvm/arm
On 2013-11-17 04:30, Christoffer Dall wrote:
Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses
in
a more generic API than the ARM-specific one and is
On 2013-11-17 04:30, Christoffer Dall wrote:
Support setting the distributor and cpu interface base addresses in
the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition to the ARM specific API.
This has the added benefit of being able to share more code in user
.
Also define some masks and shifts for the various GICH_VMCR fields.
Cc: Thomas Gleixner t...@linutronix.de
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irqchip/arm-gic.h | 14 ++
1 file changed, 14
function instead of the physical address of the
access in the VM memory map. This allows other callers unaware of
the
VM specifics, but with generic VGIC knowledge to reuse the function.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
On 2013-11-17 04:30, Christoffer Dall wrote:
Add infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding
the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS
groups
and defining the semantics of the
On 2013-11-17 04:30, Christoffer Dall wrote:
To properly access the VGIC state from user space it is very
unpractical
to have to loop through all the LRs in all register access functions.
Instead, support moving all pending state from LRs to the
distributor,
but leave active state LRs alone.
reading this
register, we can live with the difference.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Looks pretty good to me. Small note below, but otherwise:
Acked-by: Marc Zyngier marc.zyng...@arm.com
Changelog[v3]:
- Renamed read/write SGI set/clear functions
- Rely
as the current VGIC
support, and no more. For example, the active priority registers are
handled as RAZ/WI, just like setting priorities on the emulated
distributor.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
virt/kvm/arm/vgic.c | 81
...@linaro.org
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
Changelog[v2]:
- Call kvm_timer_init from kvm_arch_init_vm instead of moving the
cntvoff to
vcpu initialization, which would be redundant.
arch/arm/kvm/arm.c |2 ++
virt
On 2013-11-17 03:12, Christoffer Dall wrote:
From: Andre Przywara andre.przyw...@linaro.org
For migration to work we need to save (and later restore) the state
of
each cores virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and
export
the three needed
On 12/12/13 11:36, Peter Maydell wrote:
On 12 December 2013 09:32, Andre Przywara andre.przyw...@linaro.org wrote:
On 12/12/2013 10:23 AM, Peter Maydell wrote:
What does it mean to say that a system register for AArch64
is 32 bits given that MRS/MSR always operate on a 64 bit
register?
But
:
return -ENODEV;
Provided that you fix the above:
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
--
Jazz is not dead. It just smells funny...
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
More majordomo
space and do things in a uniform manner.
Also deprecate the older API at the same time, but backwards
compatibility will be maintained.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
---
Changelog[v4]:
- Move VGIC device
-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
---
Changelog[v4]:
- New in series
arch/arm/kvm/arm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f290b22..b92ff6d3
-by: Marc Zyngier marc.zyng...@arm.com
M.
---
Changelog[v4]:
- Factored out setting vcpu-cpu = -1 on vcpu_put to separate patch.
- Added comment to vgic_attr_regs_access and changed exit handling
path.
Changelog[v3]:
- Spelling and formatting nits
- Fill in the phys_addr
On 12/12/13 19:55, Christoffer Dall wrote:
To properly access the VGIC state from user space it is very unpractical
to have to loop through all the LRs in all register access functions.
Instead, support moving all pending state from LRs to the distributor,
but leave active state LRs alone.
Hi Christoffer,
On 12/12/13 19:55, Christoffer Dall wrote:
Implement save/restore of the VGIC state using the newer KVM Device
Control API. This requries some number of changes to existing code in
addition to actually supporting save/restore of the necessary state.
The first patches
/006133.html
It would have been good if it was done at the same time, but I'm not
even sure we have the corresponding userspace code to even test it.
So, assuming that someone will eventually implement it when QEMU/arm64
reaches the same level as its 32bit counterpart:
Acked-by: Marc Zyngier
set again in the future) and ping the
waitqueue
on turning on a VCPU using PSCI.
Reported-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
Changes[v2]:
- Use non-atomic version
christoffer.d...@linaro.org
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
virt/kvm/arm/vgic.c | 88
++---
1 file changed, 83 insertions(+), 5 deletions(-)
Changelog[v5]:
- Reworked vgic_unqueue_irqs slightly again to also consider the
ACTIVE
On 2013-12-17 05:29, Christoffer Dall wrote:
Implement save/restore of the VGIC state using the newer KVM Device
Control API. This requries some number of changes to existing code
in
addition to actually supporting save/restore of the necessary state.
The first patches (01-03) support
-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
arch/arm/kvm/arm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f290b22..b92ff6d3 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm
function instead of the physical address of the
access in the VM memory map. This allows other callers unaware of the
VM specifics, but with generic VGIC knowledge to reuse the function.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
on the exported
functions making it a bit easier to understand the init flow by only
looking at vgic.c.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
arch/arm/kvm/arm.c | 7 ---
virt/kvm/arm/vgic.c | 22 +++---
2
space and do things in a uniform manner.
Also deprecate the older API at the same time, but backwards
compatibility will be maintained.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
Documentation/virtual/kvm/api.txt | 7
From: Christoffer Dall christoffer.d...@linaro.org
Initialize the cntvoff at kvm_init_vm time, not before running the VCPUs
at the first time because that will overwrite any potentially restored
values from user space.
Cc: Andre Przywara andre.przyw...@linaro.org
Acked-by: Marc Zynger
creating the VGIC after the VCPUs have been created.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 10
arch/arm/kvm/arm.c | 1 +
include/linux/kvm_host.h
From: Andre Przywara andre.przyw...@linaro.org
For migration to work we need to save (and later restore) the state of
each core's virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
the three needed registers (control, counter, compare value).
Though they
of the VGIC.
Also define some masks and shifts for the various GICH_VMCR fields.
Cc: Thomas Gleixner t...@linutronix.de
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
include/linux/irqchip/arm-gic.h | 12
1 file changed, 12
of the attr field to be the MMIO offset as
specified in the GICv2 specs.
Missing register accesses or other changes in individual register access
functions to support save/restore of the VGIC state is added in
subsequent patches.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall
attr
KVM: arm-vgic: Support unqueueing of LRs to the dist
KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers
KVM: arm-vgic: Support CPU interface reg access
Marc Zyngier (2):
Merge tag 'vgic-migrate-for-marc' of
git://git.linaro.org/people/christoffer.dall/linux
-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/kvm/handle_exit.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 8da5606..df84d7b 100644
--- a/arch/arm64/kvm
this
register, we can live with the difference.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
virt/kvm/arm/vgic.c | 70 ++---
1 file changed, 66 insertions(+), 4 deletions(-)
diff --git
on the distributor side as well. We don't have any users of such
functionality yet and there are other inaccuracies of the GIC emulation,
so don't provide accurate synchronized access to this state just yet.
However, when the time comes, having this function should help.
Acked-by: Marc Zyngier marc.zyng
but, increasing
value of max VCPUs per-Guest can make things slower hence
we add Kconfig option to let KVM users select appropriate
max VCPUs per-Guest.
Signed-off-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Marc Zyngier
as the current VGIC
support, and no more. For example, the active priority registers are
handled as RAZ/WI, just like setting priorities on the emulated
distributor.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
virt/kvm/arm/vgic.c | 81
with Potenza core.
[maz: sanitized the commit log]
Signed-off-by: Anup Patel anup.pa...@linaro.org
Signed-off-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/uapi/asm/kvm.h| 3 ++-
arch/arm64/kvm/guest.c
into the coherent_icache_guest_page
function and flush the region if the guest SCTLR_EL1
register doesn't show the MMU and caches as being enabled.
The function also get renamed to coherent_cache_guest_page.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari
.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/include/asm/kvm_arm.h | 3 ++-
arch/arm64/kvm/sys_regs.c| 58
2 files changed, 49 insertions(+), 12 deletions(-)
diff --git
to avoid this potential disaster is to invalidate the cache
when the MMU is being turned on. For this, we hook into the SCTLR_EL1
trapping code, and scan the stage-2 page tables, invalidating the
pages/sections that have already been mapped in.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
the necessary ARMv7 bits once we reach an
agreement on arm64).
Marc Zyngier (3):
arm64: KVM: force cache clean on page fault when caches are off
arm64: KVM: trap VM system registers until MMU and caches are ON
arm64: KVM: flush VM pages before letting the guest enable caches
arch/arm/include/asm
Hi Anup,
On 20/01/14 12:00, Anup Patel wrote:
On Fri, Jan 17, 2014 at 8:33 PM, Marc Zyngier marc.zyng...@arm.com wrote:
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU
Hi Pranav,
On 21/01/14 12:17, Pranavkumar Sawargaonkar wrote:
Hi Marc,
On 20 January 2014 22:00, Anup Patel a...@brainfault.org wrote:
Hi Marc,
On Mon, Jan 20, 2014 at 7:11 PM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Anup,
On 20/01/14 12:00, Anup Patel wrote:
On Fri, Jan 17, 2014
to avoid this potential disaster is to invalidate the cache
when the MMU is being turned on. For this, we hook into the SCTLR_EL1
trapping code, and scan the stage-2 page tables, invalidating the
pages/sections that have already been mapped in.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
) and FVP model (ARMv8).
From v1 (http://www.spinics.net/lists/kvm/msg99404.html):
- Fixed AArch32 VM handling on arm64 (Reported by Anup)
- Added ARMv7 support:
* Fixed a couple of issues regarding handling of 64bit cp15 regs
* Per-vcpu HCR
* Switching of AMAIR0 and AMAIR1
Marc Zyngier (10
was made in AArch32 mode
- is_32bit: true if is_aarch32 == true and a MCR/MRC instruction
was used to perform the access (as opposed to MCRR/MRRC).
This allows a handler to cover all the possible conditions in which
a system register gets trapped.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
into the coherent_cache_guest_page
function and flush the region if the guest SCTLR
register doesn't show the MMU and caches as being enabled.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/kvm_mmu.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch
the documentation.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/kvm/coproc.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
index c5ad7ff..1a44bbe 100644
--- a/arch/arm/kvm/coproc.h
+++ b/arch/arm/kvm/coproc.h
.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/include/asm/kvm_arm.h | 3 +-
arch/arm64/include/asm/kvm_asm.h | 3 +-
arch/arm64/kvm/sys_regs.c| 99 +++-
3 files changed, 91
into the guest. This went unnoticed as we
didn;t really trap any 64bit register so far.
Placing the CRm field of the access into the CRn field of the matching
structure fixes the problem. Also update the debug feature to emit the
expected string in case of failing match.
Signed-off-by: Marc Zyngier
.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/kvm_arm.h | 3 +-
arch/arm/kvm/coproc.c | 85 ++
arch/arm/kvm/coproc_a15.c | 2 +-
arch/arm/kvm/coproc_a7.c | 2 +-
4 files changed, 73 insertions(+), 19
HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch
into the coherent_icache_guest_page
function and flush the region if the guest SCTLR_EL1
register doesn't show the MMU and caches as being enabled.
The function also get renamed to coherent_cache_guest_page.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari
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