We mirror a subset of these registers in separate variables.
Using them directly should be faster.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 10 +++---
arch/x86/kvm/lapic.h | 6 +++---
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch
APICv traps register writes, so we can't retrieve previous value and
omit timer cancelation when mode changes.
timer_mode_mask shouldn't be changing as it depends on cpuid.
Signed-off-by: Radim Krčmář
---
#define assign(a, b) (a == b ? false : (a = b, true))
arch/x86/kvm/la
C register, for performance reasons.
This leaves us with either a new framework, or exceptions ...
The latter options fits KVM's path better [1,2].
And when we already mirror a part of registers, optimizing access is
acceptable [3]. (Squashed to keep bisecters happy.)
---
Radim Krčmář
+0x14/0x20
[] system_call_fastpath+0x16/0x1b
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 10 ++
arch/x86/kvm/lapic.h | 1 +
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index b8345dd..f538b14 100644
--- a/arch/x86/kvm/lapic.c
+++ b/ar
ecific files.
The functionality looks good, so I just want verify the basic design:
why don't we emulate AMD PMU on Intel, and vice versa?
(Underlying PERF_COUNTs are identical in both.)
> V1:
> * Adopt the file layout suggested by Radim Krčmář
(I'll still advocate for more separati
2014-10-31 12:05-0400, Wei Huang:
> This patch implemented vPMU for AMD platform. The design piggybacks
> on the existing Intel structs (kvm_pmu and kvm_pmc), but only uses
> the parts of generic counters. The kvm_pmu_ops interface is also
> initialized in this patch.
>
> Signed-off-by: Wei Huang
2014-10-31 12:05-0400, Wei Huang:
> This patch converts existing pmu.c into Intel specific code and hooks
> up with the PMU interface using the following steps:
>
> - Convert pmu.c to pmu_intel.c; All public PMU functions are renamed
> and hooked up with the newly defined intel_pmu_ops.
> - Crea
2014-11-03 12:23-0600, Wei Huang:
>
>
> On 11/03/2014 11:56 AM, Radim Krčmář wrote:
> > 2014-10-31 12:05-0400, Wei Huang:
> >> Currently KVM only supports vPMU for Intel platforms. This patch set
> >> enable vPMU support for AMD platform by creating a common PM
2014-11-06 10:34+0100, Paolo Bonzini:
> On 05/11/2014 21:45, Nadav Amit wrote:
> > If I understand the SDM correctly, in such scenario (all APICs are
> > software disabled) the mode is left as the default - flat mode (see
APIC doesn't have any global mode (it is just KVM's simplification), so
when
2014-11-06 10:44+0100, Paolo Bonzini:
>
>
> On 06/11/2014 10:13, Nadav Amit wrote:
> >
> >> On Nov 6, 2014, at 10:58, Paolo Bonzini wrote:
> >>
> >> On 05/11/2014 21:31, Nadav Amit wrote:
> >>> You are correct, it does not appear clearly in the SDM, but that is what
> >>> real hardware does.
>
2014-11-06 18:46+0100, Paolo Bonzini:
> AVX instructions are just tweaks of the operand length and the alignment
> restrictions of SSE instructions, and in fact the Avx bit is just a
> duplicate of Unaligned. Drop it.
>
> Suggested-by: Nadav Amit
> Signed-off-by: Paolo Bonzini
> ---
I think th
merging them.
>
> Signed-off-by: Nadav Amit
> ---
It looks that Avx behaves a bit differently that legacy Sse, so having
it exclusive is better.
I'd make changes, but the behavior doesn't look wrong now, so
Reviewed-by: Radim Krčmář
> arch/x86/kvm/emulate.c | 44 +++
2014-11-07 18:39+0100, Paolo Bonzini:
> I think we have no clear idea of what Avx would do (I have one---same as
> Sse but make VEX prefix mandatory, see VBROADCASTSS---but I'm not sure
> it's the right one either). Let's keep these patches on hold.
Implementing Avx first makes sense, we don't wa
2014-11-10 18:35+0100, Paolo Bonzini:
> On 06/11/2014 17:45, Radim Krčmář wrote:
> > - } else if (kvm_apic_hw_enabled(apic)) {
> > + } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
> > if (kvm_apic_g
2014-11-13 12:32+0100, Andrew Jones:
> On Thu, Nov 13, 2014 at 11:44:02AM +0100, Andrew Jones wrote:
> > On Thu, Nov 13, 2014 at 09:40:41AM +0100, Andrew Jones wrote:
> > > On Thu, Nov 13, 2014 at 12:44:39AM -0200, Marcelo Tosatti wrote:
> > > > The periodic kvmclock sync can be an undesired source
2014-11-13 18:57+0100, Andrew Jones:
> On Thu, Nov 13, 2014 at 06:47:40PM +0100, Paolo Bonzini wrote:
> >
> >
> > On 13/11/2014 18:46, Radim Krčmář wrote:
> > > Yes, or add callbacks to sysfs writes that would schedule/cancel this
> > > work. (But h
2014-11-14 12:12+0100, Paolo Bonzini:
> This completes the optimization from the previous patch, by
> removing the KVM_MEM_SLOTS_NUM-iteration loop from insert_memslot.
>
> Signed-off-by: Paolo Bonzini
> ---
> virt/kvm/kvm_main.c | 39 +++
> 1 file changed, 19
2014-11-14 15:17+0100, Igor Mammedov:
> > (We'll have to change it into an interval tree, or something, if the
> > number of slots rises anyway.)
> Only if it rises to huge amount, I've played with proposed 512 memslots
> and it takes ~1 cycles which is 5% of current heapsort overhead.
> Takin
2014-11-14 15:29+0100, Paolo Bonzini:
> On 14/11/2014 14:35, Radim Krčmář wrote:
> > We are replacing in a sorted array, so the the direction of our
> > traversal doesn't change, (and we could lose one tab level here,)
> >
> > if (new->npages < mslots
;irr_pending = (vec != -1);
> + } else {
> + apic->irr_pending = false;
> + apic_clear_vector(vec, apic->regs + APIC_IRR);
> + if (apic_search_irr(apic) != -1)
> + apic->irr_pending = true;
> }
Works because apic_clear_vector() is also a compiler barrier ...
Reviewed-by: Radim Krčmář
(I hope the performance gain of irr_pending is worth its complexity.)
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2014-11-18 20:51+0100, Paolo Bonzini:
> On 16/11/2014 22:49, Nadav Amit wrote:
> > @@ -374,13 +378,15 @@ static inline void apic_clear_irr(int vec, struct
> > kvm_lapic *apic)
> > + apic->irr_pending = false;
> > + apic_clear_vector(vec, apic->regs + APIC_IRR);
> > +
pad;
struct kvm_guest_debug_arch arch;
};
and
struct kvm_guest_debug_arch {
};
mean that
sizeof(struct kvm_guest_debug) == sizeof(void *) == 8
thus
KVM_SET_GUEST_DEBUG == KVM_IA64_VCPU_SET_STACK
and KVM_SET_GUEST_DEBUG is handled before KVM_IA64_VCPU_SET_STACK.
Signed-off-
quest-scan_ioapic(struct kvm *kvm)
^_-
> +{
> +}
> +#endif
> +
Reviewed-by: Radim Krčmář
And we could clean them up as well:
---8<---
KVM: x86: remove IA64 from ioapic.c and irq_comm.c
They won't get compiled in x86 tree.
Signed-off-by: Radim Krčmář
---
ar
2014-11-21 18:05+0100, Paolo Bonzini:
> On 21/11/2014 17:19, Radim Krčmář wrote:
> > KVM: x86: remove IA64 from ioapic.c and irq_comm.c
> >
> > They won't get compiled in x86 tree.
>
> Ah no, these were already in my ia64 removal patch. I had a deja-vu
> fe
kvm_assigned_dev_kernel depends on struct kvm_irq_ack_notifier
Signed-off-by: Radim Krčmář
---
Or are we going to remove it instead? ;)
arch/x86/include/asm/kvm_host.h | 23 +++
arch/x86/kvm/Makefile | 2 +-
{virt => arch/x86}/kvm/assigned-dev.c |
2014-11-22 17:22+0100, Paolo Bonzini:
> On 21/11/2014 22:21, Radim Krčmář wrote:
> > - struct kvm_assigned_dev_kernel depends on struct kvm_irq_ack_notifier
>
> kvm_assign_device and kvm_deassign_device can also be moved to arch/x86,
> in a new assigned-dev.h header. The he
2014-11-24 11:40+0100, Jan Kiszka:
> On 2014-11-24 11:12, Paolo Bonzini wrote:
> > On 24/11/2014 05:36, nick wrote:
> >> Greetings Again Gleb and others,
> >> I am assuming in the code I am pasting below the fix me is obsolete now
> >> and I can remove it. :)
> >> Cheers Nick
> >> TP_printk("%s (0
2014-11-24 16:19-0500, Steven Rostedt:
> On Mon, 24 Nov 2014 22:00:01 +0100
> Radim Krčmář wrote:
>
> > 2014-11-24 11:40+0100, Jan Kiszka:
> > The format string has to be a string literal[1]; we could change it to
> > allow expressions[2], but what we want is almost po
et(guest_xsave, 0, sizeof(struct kvm_xsave));
> + fill_xsave((u8 *) guest_xsave->region, vcpu);
> } else {
> memcpy(guest_xsave->region,
> &vcpu->arch.guest_fpu.state->fxsave,
> @@ -3164,8 +3238,7 @@ static int kv
2014-11-24 22:49+0100, Radim Krčmář:
> 2014-11-24 16:19-0500, Steven Rostedt:
> > That wouldn't be too hard to implement.
>
> I'll look at the patch tommorrow.
The kernel part is trivial.
Most of the code is going to be in tools/lib/traceevent/event-parse.c.
I wasn&#x
2014-11-26 14:13+0100, Paolo Bonzini:
> On 26/11/2014 13:07, Radim Krčmář wrote:
> > 2014-11-24 17:43+0100, Paolo Bonzini:
> >> Userspace is expecting non-compacted format for KVM_GET_XSAVE, but
> >> struct xsave_struct might be using the compacted format. Conver
2014-11-26 14:57+0100, Paolo Bonzini:
>
>
> On 26/11/2014 14:53, Radim Krčmář wrote:
> >>> > > get_xsave = native_xrstor(guest_xsave);
> >>> > > xsave(aligned_userspace_buffer)
> >>> > > set_xsave = xrstor(
2014-11-26 09:15-0500, Steven Rostedt:
> On Wed, 26 Nov 2014 13:40:26 +0100
> Radim Krčmář wrote:
> > The kernel part is trivial.
> > Most of the code is going to be in tools/lib/traceevent/event-parse.c.
> >
> > I wasn't sure whether to
> > 1) define n
2014-11-26 17:11+0200, Nadav Amit:
> x2APIC has no registers for DFR and ICR (see Intel SDM 10.12.1.2 "x2APIC
> Register Address Space"). KVM needs to cause #GP on such accesses.
We should to take care of write to ICR2 as well.
> Fix it.
>
> Signed-off-by: Nadav Amit
> ---
> arch/x86/kvm/lapic
t; Signed-off-by: Nadav Amit
>
> ---
Reviewed-by: Radim Krčmář
> v1->v2: Cause #GP on ICR2 write access (as Radim pointed)
> ---
> arch/x86/kvm/lapic.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>
0x830 MSR is 0x300 xAPIC MMIO, which is MSR_ICR.
Signed-off-by: Radim Krčmář
---
This applies on top of Amit's
[PATCH v2] KVM: x86: Fix reserved x2apic registers
in which I noticed this minor deficit.
arch/x86/kvm/lapic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
2014-11-26 17:26+0100, Paolo Bonzini:
> On 26/11/2014 15:42, Radim Krčmář wrote:
> >> I'm not sure what is more future proof. :) I wonder if native_xrstor
> >> could be a problem the day XRSTORS actually sets/restores MSRs as the
> >> processor documentati
2014-11-26 19:01+0200, Nadav Amit:
> Sorry for the late and long reply, but I got an issue with the new version
> (and my previous version as well). Indeed, the SDM states that DFR should
> be the same for enabled CPUs, and that the BIOS should get all CPUs in
> either xAPIC or x2APIC. Yet, there i
D and MOVNTI. MOVBE is the most blunt example, since it may be
> emulated by the host regardless of MMIO.
>
> The fix introduces a new group for handling such instructions, marking mod3 as
> illegal instruction.
>
> Signed-off-by: Nadav Amit
> ---
Reviewed-by: Radim Krčmá
2014-11-27 05:30-0800, Phil White:
> This introduces a list of entries which associate a function pointer of
> kvm_hc_type to a hypercall number and allows the ability to register and
> unregister entries. In addition, it also allows the ability to retrieve a
> function pointer of kvm_hc_type for
uster wasn't
set up correctly.
This patch extends x2APIC support back to the logical_map's limit, and
keeps the CVE fixed as messages for non-present APICs are dropped.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 11 ++-
arch/x86/kvm/lapic.h | 2 --
2 files change
False from kvm_irq_delivery_to_apic_fast() means that we don't handle it
in the fast path, but we still return false in cases that were perfectly
handled, fix that.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
x2apic allows destinations > 0xff and we don't want them delivered to
lower APICs. They are correctly handled by doing nothing.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch
n the interrupt address are present and enabled to receive
interrupts.
We could warn on top of that.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index e0e5642..e8ad09d 100644
--- a/arch/x8
The interesting one is [3/4], which improves upon a previous CVE fix;
we also handle logical destination wrapping in it, so [2/4] does the
same for physical; and to make it nicer, [1/4] removes a condition.
[4/4] makes our fast path return true when the message was handled.
Radim Krčmář (4
2014-11-27 21:53+0200, Nadav Amit:
> Radim Krčmář wrote:
> > - new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
> > - new->lid_mask = 0x;
> > + new->cid_mask = new->lid_mask = 0x;
> You set c
2014-11-27 22:39+0200, Nadav Amit:
> Radim Krčmář wrote:
>
> > 2014-11-27 21:53+0200, Nadav Amit:
> >> Radim Krčmář wrote:
> >>> - new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
> >>> - new->lid_m
2014-11-27 23:45+0200, Nadav Amit:
> Radim Krčmář wrote:
> > 2014-11-26 19:01+0200, Nadav Amit:
> >> Sorry for the late and long reply, but I got an issue with the new version
> >> (and my previous version as well). Indeed, the SDM states that DFR should
> >&g
They can't be violated now, but we think against the infinite thing.
Signed-off-by: Radim Krčmář
---
I realized it could make a separate patch as well,
which might be more convenient.
arch/x86/kvm/lapic.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arc
treat hc_nr as a 4 character ID rather
> than a particular digit.
(This would probably solve the situation in practice, but the conflict
is still there, so design hasn't improved.)
> "The generation of random numbers is too important to be left to
> chance." -Robert R. Covey
2014-12-01 17:30+0100, Paolo Bonzini:
> On 27/11/2014 23:26, Radim Krčmář wrote:
> > We can't deliver xAPIC and x2APIC broadcasts/logical messages at the
> > same time with current KVM and this patch just switches the working case
> > in favour of x2APIC, which is
2014-12-01 17:22+0100, Paolo Bonzini:
> On 27/11/2014 20:03, Radim Krčmář wrote:
> > The interesting one is [3/4], which improves upon a previous CVE fix;
> > we also handle logical destination wrapping in it, so [2/4] does the
> > same for physical; and to make it n
(tl;dr version at the bottom)
2014-12-01 15:43-0800, Phil White:
> On Mon, Dec 1, 2014 at 5:47 AM, Radim Krčmář wrote:
> > 2014-11-28 17:29-0800, Phil White:
> >> Good questions.
> >>
> >> One thing that prompted this code is the presence and prolife
d-off-by: Igor Mammedov
> ---
Fast ... it looks that we don't even want to transfort the list-in-array
into a tree-in-array to have multiplication instead of division.
Reviewed-by: Radim Krčmář
(Actually, all patches.)
> include/linux/kvm_host.h | 34 ++
&
2014-12-02 19:45+0100, Paolo Bonzini:
> On 02/12/2014 18:33, Radim Krčmář wrote:
> >> > +while (start < end) {
> >> > +slot = start + (end - start) / 2;
> >> > +
> >> > +if (gfn >= memslots[slot].bas
contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0.)
> ++*nent;
Forcing a change of the XSAVES implementation is a likely purpose of
this patch and it is correct after changing the ecx handling, so then,
Reviewed-by: Radim Krčmář
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2014-12-03 09:04+0100, Paolo Bonzini:
> On 03/12/2014 00:05, Radim Krčmář wrote:
> > 2014-12-02 14:09+0100, Paolo Bonzini:
> >> + } else {
> >> + if (entry[i].eax == 0 || !(supported & mask))
> >> +
2014-12-02 19:21+0800, Wanpeng Li:
> Exporse intel xsaves feature to guest.
0xD.1:ebx ought to be non-zero with XSAVES, even if IA32_XSS is known to
be 0, so we'll need to set it after Paolo's patch.
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/cpuid.c | 3 ++-
> 1 file changed, 2 insertion
2014-12-03 14:40+0100, Paolo Bonzini:
> This is the size of the XSAVES area. This completes guest support
> for XSAVES (with no support yet for supervisor states, i.e. XSS == 0
> always in guests for now).
>
> Suggested-by: Radim Krčmář
> Signed-off-by: Paolo Bonzini
> --
7;t a subset of XCOMP_BV.
Make it so.
SDM: XRSTORS Exceptions
#GP If a bit in the XCOMP_BV field in the XSAVE header is 0 and the
corresponding bit in the XSTATE_BV field is 1.
(Also in SDM: 13.11 OPERATION OF XRSTORS)
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/x86.c | 4 +++-
1 file chan
2014-12-04 19:11+0800, Wanpeng Li:
> The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
> f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
> mentioned is older than SDM.
>
> EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
> states enabled by XCR0|I
gt; Signed-off-by: Wanpeng Li
> ---
Reviewed-by: Radim Krčmář
(Nested part later.)
> v1 -> v2:
> * use | (bitwise or) instead of II (logical or)
>
> arch/x86/kvm/cpuid.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/cp
2014-12-04 14:43+0100, Paolo Bonzini:
> On 03/12/2014 19:45, Radim Krčmář wrote:
> > Btw, we don't care about crashers from userspace?
>
> We do, but they're taken care of by
>
> if (xstate_bv & ~kvm_supported_xcr0())
>
2014-12-04 16:49+0100, Paolo Bonzini:
> On 04/12/2014 14:14, Radim Krčmář wrote:
> > 2014-12-04 19:11+0800, Wanpeng Li:
> >> The the value of EBX should represent the size of XCR0 related XSAVE
> >> area since IA32_XSS is not used currently.
> >
> > True, b
XSAVE
> but the kernel will pass it to XRSTORS, and we need to convert back.
>
> Fixes: f31a9f7c71691569359fa7fb8b0acaa44bce0324
> Cc: Fenghua Yu
> Cc: sta...@vger.kernel.org
> Cc: H. Peter Anvin
> Reported-by: Nadav Amit
> Tested-by: Nadav Amit
> Signed-off-by: Paolo
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add logic to get/set the XSS model-specific register.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> @@ -2896,7 +2919,8 @@ static __init int setup_vmcs_c
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Initialize the XSS exit bitmap. It is zero so there should be no XSAVES
> or XRSTORS exits.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
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To unsubscribe
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add logic to get/set the XSS model-specific register.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> @@ -2896,7 +2919,8 @@ static __init int setup_vmcs_c
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add vmcs12 support for xsaves.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> + case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
> +
i
> ---
Reviewed-by: Radim Krčmář
> --- a/arch/x86/include/asm/vmx.h
> +++ b/arch/x86/include/asm/vmx.h
> @@ -69,6 +69,7 @@
> #define SECONDARY_EXEC_PAUSE_LOOP_EXITING0x0400
> #define SECONDARY_EXEC_ENABLE_INVPCID0x1000
> #define SECONDAR
Simple replacement where possible.
Saves us problematic access to the structure and allows optimalizations
and bug fixes to take place.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 7 ---
kernel/events/core.c | 6 +++---
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git
2013-10-17 12:39+0200, Paolo Bonzini:
> Il 17/10/2013 12:10, Radim Krčmář ha scritto:
> > Simple replacement where possible.
> > Saves us problematic access to the structure and allows optimalizations
> > and bug fixes to take place.
>
> I think you should introduce thi
We can cancel deferred static_key_slow_dec() instead of increasing
.enabled.counter.
Timer now won't fire before 'timeout' since the last increase, so this patch
further stabilizes the case of frequent switching.
Signed-off-by: Radim Krčmář
---
kernel/jump_label.c | 3 ++-
1
I wrote this on Tuesday and then moved to higher priority work, but
returned with enough courage to post a different first part.
The first part was tested on amd64, s390x and ppc64, the rest also on
armv7.
Applies to next-20131206 and v3.13-rc3.
Radim Krčmář (5):
static_key: add a section for
-by: Radim Krčmář
---
More general solution would use compile-time magic to generate an array
of pointers to deferred structures, but I am not sure if it is
acceptable and possible.
Worse approach added an unload_callback_list to the struct module.
Callbacks of type void (*)(void *) were
/dev/null -monitor stdio &
sleep 0.5
until modprobe -rv kvm_intel 2>/dev/null; do :; done
Signed-off-by: Radim Krčmář
---
I decided not to post a patch that uses __deferred_key in kernel/module init,
so these three functions might seem like an overkill.
kernel/jump_label.c | 22
Complement the static_key_slow_dec_deferred().
This avoids asymmetrical API, and prepares us for future optimizations
and bug fixes.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/lapic.c | 7 ---
include/linux/jump_label_ratelimit.h | 5 +
kernel/events/core.c
() is kept and we skip an equal amount of
static_key_slow_inc_deferred().
Signed-off-by: Radim Krčmář
---
include/linux/jump_label_ratelimit.h | 1 +
kernel/jump_label.c | 17 +++--
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/inc
2013-12-12 21:36+0100, Paolo Bonzini:
> From: Gleb Natapov
>
> A guest can cause a BUG_ON() leading to a host kernel crash.
> When the guest writes to the ICR to request an IPI, while in x2apic
> mode the following things happen, the destination is read from
> ICR2, which is a register that the g
2013-12-13 18:25+0100, Paolo Bonzini:
> Il 13/12/2013 17:07, Radim Krčmář ha scritto:
> >This bug can only be hit when the destination cpu is > 256, so the
> >request itself is buggy -- we don't support that many in kvm and it
> >would crash when ini
2013-12-14 11:46+0200, Gleb Natapov:
> On Fri, Dec 13, 2013 at 05:07:54PM +0100, Radim Krčmář wrote:
> > 2013-12-12 21:36+0100, Paolo Bonzini:
> > > From: Gleb Natapov
> > >
> > > A guest can cause a BUG_ON() leading to a host kernel crash.
> > > W
2013-12-16 14:16+0200, Gleb Natapov:
> On Mon, Dec 16, 2013 at 01:01:10PM +0100, Radim Krčmář wrote:
> > > > - Where does the 'only one supported cluster' come from?
> > > >
> > > "only one supported cluster" comes from 8 bit cpuid limita
2013-12-16 13:55+0100, Radim Krčmář:
> 2013-12-16 14:16+0200, Gleb Natapov:
> > On Mon, Dec 16, 2013 at 01:01:10PM +0100, Radim Krčmář wrote:
> > > > > - Where does the 'only one supported cluster' come from?
> > > > >
> > > > &quo
indow remains closed until
the next exit.
Fix this by making KVM_REQ_EVENT request in the iret handler.
Signed-off-by: Radim Krčmář
---
(btw. kvm-unit-tests weren't executed on SVM since Nov 2010, at least)
arch/x86/kvm/svm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/sv
2014-01-17 12:18-0800, Greg KH:
> On Fri, Jan 17, 2014 at 08:52:42PM +0100, Radim Krčmář wrote:
> > We should open NMI window right after an iret, but SVM exits before it.
> > We wanted to single step using the trap flag and then open it.
> > (or we could emulate the iret ins
KVM_CAP_INTERNAL_ERROR_DATA condition on printf.
(partially improved by bb44e0d12df70 and ba4047cf848a3 in the past)
Signed-off-by: Radim Krčmář
---
kvm-all.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/kvm-all.c b/kvm-all.c
index 0bfb060..0a91d8e 100644
--- a/kvm-all.c
+++ b/kvm
2014-03-04 23:35+0530, ratheesh kannoth:
> Could you please help me understand below variables ? i found
> it in "struct kvm_vcpu"
>
> char *host_fx_image;
> char *guest_fx_image;
Commit b114b0804df7131cb6764b948c1c530c834fa3c0 explains them.
(How does the existence depe
2014-03-07 12:42+0100, Paolo Bonzini:
> When not running in guest-debug mode (i.e. the guest controls the debug
> registers, having to take an exit for each DR access is a waste of time.
> If the guest gets into a state where each context switch causes DR to be
> saved and restored, this can take a
2014-03-07 12:42+0100, Paolo Bonzini:
> When not running in guest-debug mode, the guest controls the debug
> registers and having to take an exit for each DR access is a waste
> of time. If the guest gets into a state where each context switch
> causes DR to be saved and restored, this can take aw
2014-03-09 21:07+0100, Paolo Bonzini:
> Il 09/03/2014 19:28, Radim Krčmář ha scritto:
> >>> /*
> >>> + * Do this here before restoring debug registers on the host. And
> >>> + * since we do this before handling the vmexit, a DR access vmexit
> >
2014-03-09 21:12+0100, Paolo Bonzini:
> Il 09/03/2014 19:26, Radim Krčmář ha scritto:
> >> +
> >> + /*
> >> + * No more DR vmexits; force a reload of the debug registers
> >> + * and reenter on this instruction. The next vmex
run with dirty debug registers
> KVM: nVMX: Allow nested guests to run with dirty debug registers
> KVM: svm: set/clear all DR intercepts in one swoop
> KVM: svm: Allow the guest to run with dirty debug registers
All patches,
Reviewed-by: Radim Krčmář
This series is good even without v
when needed. This fixes BSOD in Windows 2008.
Cc:
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/svm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 64d9bb9..f676c18 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
2014-03-11 22:05-0300, Marcelo Tosatti:
> On Tue, Mar 11, 2014 at 07:11:18PM +0100, Radim Krčmář wrote:
> > We always disable cr8 intercept in its handler, but only re-enable it
> > if handling KVM_REQ_EVENT, so there can be a window where we do not
> > intercept cr8 wr
2014-03-13 15:52+0200, Gleb Natapov:
> On Wed, Mar 12, 2014 at 06:20:01PM +0100, Paolo Bonzini wrote:
> > Il 12/03/2014 11:40, Radim Krčmář ha scritto:
> > >2014-03-11 22:05-0300, Marcelo Tosatti:
> > >>On Tue, Mar 11, 2014 at 07:11:18PM +0100, Radim Krčmář wrote
2014-03-21 10:28+0100, Paolo Bonzini:
> We will reuse it to process a nonzero IRR that is passed to KVM_SET_IRQCHIP.
>
> Reviewed-by: Alex Williamson
> Signed-off-by: Paolo Bonzini
> ---
> v1->v2:
> more comments
> change argument name from level to irq_level
>
> virt/kvm/ioa
2014-03-23 09:44+0100, Paolo Bonzini:
> Il 21/03/2014 19:58, Radim Krčmář ha scritto:
> >>> + /*
> >>> + * Return 0 for coalesced interrupts; for edge-triggered interrupts,
> >>> + * this only happens if a previous edge has not been delivered due
> >&
2014-03-21 10:28+0100, Paolo Bonzini:
> After the previous patches, an interrupt whose bit is set in the IRR
> register will never be in the LAPIC's IRR and has never been injected
> on the migration source. So inject it on the destination.
>
> This fixes migration of Windows guests without HPET
. Please review.
>
> Paolo
>
> v1->v2:
> more comments in patch 3
> change argument name in patch 3 from level to irq_level
> use IOAPIC_NUM_PINS in patch 4 as a limit to for_each_set_bit
> remove debug printk in patch 4
Nice solution to
2014-03-24 19:14+0100, Paolo Bonzini:
> Il 24/03/2014 18:58, Radim Krčmář ha scritto:
> > I'd prefer 'ioapic->irr = 0' here ...)
>
> The point is that "ioapic->irr = 0" is overriding the previous
> memcpy, because state->irr is used as argu
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