Re: [PATCH v2 07/18] nvdimm: reserve address range for NVDIMM

Hi Eduardo, Thank you for reviewing my patches. On 08/29/2015 01:25 AM, Eduardo Habkost wrote: On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote: NVDIMM reserves all the free range above 4G to do: - Persistent Memory (PMEM) mapping - implement NVDIMM ACPI device _DSM method

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/31/2015 03:46 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 10:53:58AM +0800, Xiao Guangrong wrote: On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even when we skip data decoding, MMIO is slightly slower than port IO because it uses the page-tables, so the CPU must do

Re: [GIT PULL] Early batch of KVM changes for 4.3 merge window

Linus, I am sorry for the annoyance. On 09/01/2015 08:47 AM, Linus Torvalds wrote: Hmm: On Fri, Aug 14, 2015 at 4:57 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: Xiao Guangrong (9): KVM: MMU: fully check zero bits for sptes The above commit causes an annoying new compiler w

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/31/2015 07:27 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 04:32:52PM +0800, Xiao Guangrong wrote: On 08/31/2015 03:46 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 10:53:58AM +0800, Xiao Guangrong wrote: On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even when we skip data decoding, MMIO is slightly slower than port IO because it uses the page-tables, so the CPU must do a pagewalk on each access. This overhead is normally masked by using the TLB cache: but not so for KVM MMIO, where PTEs

Re: [Qemu-devel] [PATCH v2 06/18] pc: implement NVDIMM device abstract

On 08/25/2015 10:57 PM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:51:59PM +0800, Xiao Guangrong wrote: +static void set_file(Object *obj, const char *str, Error **errp) +{ +PCNVDIMMDevice *nvdimm = PC_NVDIMM(obj); + +if (nvdimm-file) { +g_free(nvdimm-file

Re: [Qemu-devel] [PATCH v2 07/18] nvdimm: reserve address range for NVDIMM

On 08/25/2015 11:12 PM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote: diff --git a/hw/mem/nvdimm/pc-nvdimm.c b/hw/mem/nvdimm/pc-nvdimm.c index a53d235..7a270a8 100644 --- a/hw/mem/nvdimm/pc-nvdimm.c +++ b/hw/mem/nvdimm/pc-nvdimm.c @@ -24,6 +24,19

Re: [PATCH] target-i386: enable cflushopt/clwb/pcommit instructions

On 08/22/2015 12:05 AM, Eduardo Habkost wrote: On Fri, Aug 21, 2015 at 01:05:12PM +0800, Xiao Guangrong wrote: These instructions are used by NVDIMM drivers and the specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Let them be enabled

Re: [PATCH v2 08/18] nvdimm: init backend memory mapping and config data area

On 08/26/2015 12:03 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:01PM +0800, Xiao Guangrong wrote: The parameter @file is used as backed memory for NVDIMM which is divided into two parts if @dataconfig is true: s/dataconfig/configdata/ Stupid typo, sorry. @@ -76,13 +109,87

Re: [PATCH v2 10/18] nvdimm: init the address region used by DSM method

On 08/26/2015 12:11 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:03PM +0800, Xiao Guangrong wrote: @@ -257,14 +258,91 @@ static void build_nfit_table(GSList *device_list, char *buf) } } +struct dsm_buffer { +/* RAM page. */ +uint32_t handle; +uint8_t arg0[16

Re: [PATCH v2 15/18] nvdimm: support NFIT_CMD_GET_CONFIG_SIZE function

On 08/26/2015 12:24 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:08PM +0800, Xiao Guangrong wrote: Function 4 is used to get Namespace lable size s/lable/label/ Stupid me, will fix the change log. -- To unsubscribe from this list: send the line unsubscribe kvm in the body

Re: [Qemu-devel] [PATCH v2 13/18] nvdimm: build namespace config data

On 08/26/2015 12:16 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:06PM +0800, Xiao Guangrong wrote: +#ifdef NVDIMM_DEBUG +#define nvdebug(fmt, ...) fprintf(stderr, nvdimm: fmt, ## __VA_ARGS__) +#else +#define nvdebug(...) +#endif The following allows the compiler to check format

Re: [PATCH v2 14/18] nvdimm: support NFIT_CMD_IMPLEMENTED function

On 08/26/2015 12:23 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:52:07PM +0800, Xiao Guangrong wrote: @@ -306,6 +354,18 @@ struct dsm_buffer { static ram_addr_t dsm_addr; static size_t dsm_size; +struct cmd_out_implemented { QEMU coding style uses typedef struct {} CamelCase

Re: [Qemu-devel] [PATCH v2 00/18] implement vNVDIMM

On 08/26/2015 12:26 AM, Stefan Hajnoczi wrote: On Fri, Aug 14, 2015 at 10:51:53PM +0800, Xiao Guangrong wrote: Changlog: - Use litten endian for DSM method, thanks for Stefan's suggestion - introduce a new parameter, @configdata, if it's false, Qemu will build a static and readonly

[PATCH 0/9] KVM: x86: enable cflushopt/clwb/pcommit and simplify code

these three instructions for guest patch 4 ~ patch 9 simplify current VMX code Xiao Guangrong (9): KVM: MMU: fix use uninitialized value KVM: x86: allow guest to use cflushopt anc clwb KVM: x86: add pcommit support KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02() KVM: VMX: simplify

[PATCH 4/9] KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02()

SECONDARY_EXEC_RDTSCP set for L2 guest comes from vmcs12 Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index b526c61..f7a721e 100644 --- a/arch/x86

[PATCH 8/9] KVM: VMX: introduce set_clear_2nd_exec_ctrl()

It's used to clean up the code Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 42 +++--- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4f238b7..58f7b89

[PATCH 7/9] KVM: VMX: unify SECONDARY_VM_EXEC_CONTROL update

Unify the update in vmx_cpuid_update() Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 0d68140..4f238b7 100644 --- a/arch

[PATCH 5/9] KVM: VMX: simplify rdtscp handling in vmx_cpuid_update()

if vmx_rdtscp_supported() is true SECONDARY_EXEC_RDTSCP must have already been set in current vmcs by vmx_secondary_exec_control() Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff

[PATCH 3/9] KVM: x86: add pcommit support

Pass PCOMMIT CPU feature to guest to enable PCOMMIT instruction Currently we do not catch pcommit instruction for L1 guest and allow L1 to catch this instruction for L2 The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao

[PATCH 2/9] KVM: x86: allow guest to use cflushopt anc clwb

Pass its CPU feature to guest to enable them in guest These are needed by nvdimm drivers The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/cpuid.c | 2 +- 1

[PATCH 1/9] KVM: MMU: fix use uninitialized value

root, leaf; It's true as shadow_walk_init() may stop the loop Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 70c375f..a8a5b8d 100644 --- a/arch

[PATCH 6/9] KVM: VMX: simplify invpcid handling in vmx_cpuid_update()

-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 99f638e..0d68140 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -8684,20 +8684,13

[PATCH 9/9] KVM: VMX: drop rdtscp_enabled field

Check cpuid bit instead of it Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/cpuid.h | 8 arch/x86/kvm/vmx.c | 19 ++- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index

[PATCH] target-i386: enable cflushopt/clwb/pcommit instructions

These instructions are used by NVDIMM drivers and the specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Let them be enabled on Broadwell on default Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- target-i386/cpu.c | 14

[PATCH v2 01/18] acpi: allow aml_operation_region() working on 64 bit offset

Currently, the offset in OperationRegion is limited to 32 bit, extend it to 64 bit so that we can switch SSDT to 64 bit in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 2 +- include/hw/acpi/aml-build.h | 2 +- 2 files changed, 2

[PATCH v2 09/18] nvdimm: build ACPI NFIT table

are not needed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/acpi-build.c | 3 + hw/mem/Makefile.objs | 2 +- hw/mem/nvdimm/acpi.c | 285 + hw/mem/nvdimm/internal.h | 29 + hw/mem/nvdimm/pc-nvdimm.c

[PATCH v2 05/18] acpi: add aml_create_field

Implement CreateField term which are used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 14 ++ include/hw/acpi/aml-build.h | 1 + 2 files changed, 15 insertions(+) diff --git a/hw/acpi/aml-build.c

[PATCH v2 03/18] acpi: add aml_derefof

Implement DeRefOf term which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 8 include/hw/acpi/aml-build.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml

[PATCH v2 07/18] nvdimm: reserve address range for NVDIMM

NVDIMM reserves all the free range above 4G to do: - Persistent Memory (PMEM) mapping - implement NVDIMM ACPI device _DSM method Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/pc.c | 12 ++-- hw/mem/nvdimm/pc-nvdimm.c | 13 + include

[PATCH v2 06/18] pc: implement NVDIMM device abstract

device for the guest Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- default-configs/i386-softmmu.mak | 1 + default-configs/x86_64-softmmu.mak | 1 + hw/Makefile.objs | 2 +- hw/mem/Makefile.objs | 1 + hw/mem/nvdimm/pc-nvdimm.c | 99

[PATCH v2 08/18] nvdimm: init backend memory mapping and config data area

on NVDIMM device on host - the raw PMEM device on host, e,g /dev/pmem0 Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/pc-nvdimm.c | 109 - include/hw/mem/pc-nvdimm.h | 7 +++ 2 files changed, 115 insertions(+), 1

[PATCH v2 17/18] nvdimm: support NFIT_CMD_SET_CONFIG_DATA

Function 6 is used to set Namespace Label Data Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 40 1 file changed, 40 insertions(+) diff --git a/hw/mem/nvdimm/acpi.c b/hw/mem/nvdimm/acpi.c index 517d710..283228d

[PATCH v2 15/18] nvdimm: support NFIT_CMD_GET_CONFIG_SIZE function

Function 4 is used to get Namespace lable size Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 70 1 file changed, 70 insertions(+) diff --git a/hw/mem/nvdimm/acpi.c b/hw/mem/nvdimm/acpi.c index 20aefce

[PATCH v2 16/18] nvdimm: support NFIT_CMD_GET_CONFIG_DATA

Function 5 is used to get Namespace Label Data Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 32 1 file changed, 32 insertions(+) diff --git a/hw/mem/nvdimm/acpi.c b/hw/mem/nvdimm/acpi.c index 0a5f2c2..517d710 100644

[PATCH v2 18/18] nvdimm: add maintain info

Add NVDIMM maintainer Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 978b717..86786e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -793,6 +793,12 @@ M: Jiri Pirko j

[PATCH v2 13/18] nvdimm: build namespace config data

If @configdata is false, Qemu will build a static and readonly namespace in memory and use it serveing for DSM GET_CONFIG_SIZE/GET_CONFIG_DATA requests Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/Makefile.objs | 3 +- hw/mem/nvdimm/acpi.c | 10 ++ hw

[PATCH v2 11/18] nvdimm: build ACPI nvdimm devices

handle, arg0, arg1 and arg2. Arg3 is conditionally saved in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/acpi-build.c | 2 + hw/mem/nvdimm/acpi.c | 130 - include/hw/mem/pc-nvdimm.h | 2 + 3 files

[PATCH v2 12/18] nvdimm: save arg3 for NVDIMM device _DSM method

Check if the function (Arg2) has additional input info (arg3) and save the info if needed We only do the save on NVDIMM device since we are not going to support any function on root device Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 73

[PATCH v2 14/18] nvdimm: support NFIT_CMD_IMPLEMENTED function

currently only allow to access device's Label Namespace Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 152 +++ 1 file changed, 152 insertions(+) diff --git a/hw/mem/nvdimm/acpi.c b/hw/mem/nvdimm/acpi.c index

[PATCH v2 10/18] nvdimm: init the address region used by DSM method

-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/nvdimm/acpi.c | 80 ++- hw/mem/nvdimm/internal.h | 1 + hw/mem/nvdimm/pc-nvdimm.c | 2 +- 3 files changed, 81 insertions(+), 2 deletions(-) diff --git a/hw/mem/nvdimm/acpi.c b/hw

[PATCH v2 02/18] i386/acpi-build: allow SSDT to operate on 64 bit

allocate free space within this region which is used by NVDIMM _DSM method Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/acpi-build.c | 4 ++-- hw/i386/acpi-dsdt.dsl | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi

[PATCH v2 00/18] implement vNVDIMM

nd.pmem.ko You can see /dev/pmem1 appears == TODO == 1) NVDIMM NUMA support 2) NVDIMM hotplug support Xiao Guangrong (18): acpi: allow aml_operation_region() working on 64 bit offset i386/acpi-build: allow SSDT to operate on 64 bit acpi: add aml_derefof acpi: add aml_sizeof acpi

[PATCH v2 04/18] acpi: add aml_sizeof

Implement SizeOf term which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 8 include/hw/acpi/aml-build.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml

Re: [PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

On 08/05/2015 06:12 PM, Paolo Bonzini wrote: On 05/08/2015 06:04, Xiao Guangrong wrote: - for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) + for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { + leaf = iterator.level; + + if (!root

[PATCH 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10

Re: [PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

CCed Pavel Shirshov ru.pc...@gmail.com Sorry, git tool missed to CC mail to the person tagged with Reported-by and Tested-by. :( On 08/04/2015 06:59 PM, Xiao Guangrong wrote: Current code validating mmio #PF is buggy, it was spotted by Pavel Shirshov, the bug is that qemu complained with KVM

[PATCH 1/9] KVM: MMU: fix validation of mmio page fault

check will be introduced in later patches Reported-by: Pavel Shirshov ru.pc...@gmail.com Tested-by: Pavel Shirshov ru.pc...@gmail.com Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions

[PATCH 8/9] KVM: MMU: fully check reserved bits for sptes

is the real bug is detected Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 3f9ce29..6b0e9c9 100644 --- a/arch

[PATCH 7/9] KVM: MMU: introduce is_shadow_rsvd_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 28

[PATCH 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

[PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

pte to check sptes Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM: MMU: split reset_rsvds_bits_mask_ept KVM: MMU: introduce the framework

[PATCH 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check reserved bits on host shadow page table entries Signed-off-by: Xiao Guangrong guangrong.x

[PATCH 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 26

[PATCH 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 14

[PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check reserved bits on shadow page tables Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 09:23 PM, Paolo Bonzini wrote: On 04/08/2015 15:10, Xiao Guangrong wrote: This should be cpu_has_nx, I think. cpu_has_nx() checks the feature on host CPU, however, this is the shadow page table which completely follow guest's features. E.g, if guest does not execution

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 08:14 PM, Paolo Bonzini wrote: On 04/08/2015 12:59, Xiao Guangrong wrote: +/* + * the page table on host is the shadow page table for the page + * table in guest or amd nested guest, its mmu features completely + * follow the features in guest. + */ +void

Re: [PATCH] KVM: MTRR: Use default type for non-MTRR-covered gfn before WARN_ON

On 08/05/2015 12:58 AM, Alex Williamson wrote: The patch was munged on commit to re-order these tests resulting in excessive warnings when trying to do device assignment. Return to original ordering: https://lkml.org/lkml/2015/7/15/769 Reviewed-by: Xiao Guangrong guangrong.x

[PATCH v2 0/9] KVM: MMU: fix and improve validation of mmio page fault

the reserved bits on hardware but also check other bits that spte never used Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM: MMU: split

[PATCH v2 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check host shadow page table entries as well Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com

[PATCH v2 1/9] KVM: MMU: fix validation of mmio page fault

check will be introduced in later patches Reported-by: Pavel Shirshov ru.pc...@gmail.com Tested-by: Pavel Shirshov ru.pc...@gmail.com Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions

[PATCH v2 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10

[PATCH v2 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 14

[PATCH v2 7/9] KVM: MMU: introduce is_shadow_zero_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 28

[PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

but also the bits spte never used, then dump the shadow page table hierarchy if the real bug is detected Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git

[PATCH v2 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 26

[PATCH v2 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

[PATCH v2 6/9] KVM: MMU: introduce the framework to check zero bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check zero bits on shadow page tables The zero bits on sptes include not only reserved bits on hardware but also the bits sptes nerve used Signed-off-by: Xiao

Re: KVM: unknown exit, hardware reason 31

On 07/31/2015 06:51 AM, Pavel Shirshov wrote: Hi Xiao, I've been testing your patch since Jul, 27. Everything works perfectly with it. There are no EPT messages in dmesg output anymore. Also all VMs work as expected: no paused VMs, no code 31 error. Let me know if you need any additional

Re: [Qemu-devel] [PATCH 00/16] implement vNVDIMM

On 07/03/2015 02:11 AM, Paolo Bonzini wrote: On 02/07/2015 20:01, Xiao Guangrong wrote: Thanks for your review, Stefan and Paolo! On 07/02/2015 05:52 PM, Paolo Bonzini wrote: On 02/07/2015 11:20, Stefan Hajnoczi wrote: Currently, the NVDIMM driver has been merged into upstream Linux

Re: KVM: unknown exit, hardware reason 31

I guess it happened on this scenario: 1. QEMU drops mmio region 2. invalidate all mmio sptes 3. VCPU 0 KVMVCPU 1 access the invalid mmio spte page reclaim zap shadow page

Re: [PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

On 07/23/2015 01:56 PM, Paolo Bonzini wrote: On 15/07/2015 21:25, Xiao Guangrong wrote: From: Xiao Guangrong guangrong.x...@intel.com Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind

Re: [PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

On 07/23/2015 02:21 PM, Paolo Bonzini wrote: On 16/07/2015 06:10, Alex Williamson wrote: On Thu, 2015-07-16 at 03:25 +0800, Xiao Guangrong wrote: From: Xiao Guangrong guangrong.x...@intel.com Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead

Re: [PATCH] KVM: x86: rename quirk constants to KVM_X86_QUIRK_*

On 07/23/2015 02:26 PM, Paolo Bonzini wrote: Make them clearly architecture-dependent; the capability is valid for all architectures, but the argument is not. Reviewed-by: Xiao Guangrong guangrong.x...@linux.intel.com Okay, i saw you already have adjusted and merged my patchset, thanks

[PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

From: Xiao Guangrong guangrong.x...@intel.com Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead Signed-off-by: Xiao Guangrong guangrong.x...@intel.com --- arch/x86/kvm/mtrr.c | 21 - 1 file changed, 20 insertions(+), 1 deletion

[PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

From: Xiao Guangrong guangrong.x...@intel.com Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind of firmware happy This quirk can be dropped by using KVM_ENABLE_CAP API with KVM_CAP_DISABLE_QUIRKS

[PATCH 2/3] KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type

From: Xiao Guangrong guangrong.x...@intel.com kvm_mtrr_get_guest_memory_type never returns -1 which is implied in the current code since if @type = -1 (means no MTRR contains the range), iter.partial_map must be true Simplify the code to indicate this fact Signed-off-by: Xiao Guangrong

Re: MTRR setup in OVMF [was: PATCH v3 01/10 KVM: MMU: fix decoding cache type from MTRR]

Hi, I have posted the pachset to make OVMF happy and have CCed you guys, could you please check it if it works for you? On 07/15/2015 05:15 AM, Paolo Bonzini wrote: The long delay that Alex reported (for the case when all guest memory was set to UC up-front) is due to the fact that the SEC

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 03:32 PM, Paolo Bonzini wrote: I'm seeing a significant regression in boot performance on Intel hardware with assigned devices that bisects back to this patch. There's a long delay with Seabios between the version splash and execution of option ROMs, and a _very_ long delay with

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 11:13 PM, Paolo Bonzini wrote: On 13/07/2015 16:45, Xiao Guangrong wrote: +/* MTRR is completely disabled, use UC for all of physical memory. */ +if (!(mtrr_state-enabled 0x2)) +return MTRR_TYPE_UNCACHABLE; actually disappears in commit fa61213746a7 (KVM: MTRR

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 01:33 AM, Alex Williamson wrote: On Wed, 2015-05-13 at 14:42 +0800, Xiao Guangrong wrote: There are some bugs in current get_mtrr_type(); 1: bit 1 of mtrr_state-enabled is corresponding bit 11 of IA32_MTRR_DEF_TYPE MSR which completely control MTRR's enablement

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/10/2015 06:47 PM, Paolo Bonzini wrote: On 10/07/2015 03:19, Xiao Guangrong wrote: yes, this is correct. QEMU still does not have support for disabling quirks, so gCR0.CD is currently hidden on SVM. I would like to include this series in 4.2, while for 4.3 I will disable the quirk

Re: [PATCH] KVM: svm: remove KVM_QUIRK_CD_NW_CLEARED quirk

tables. This behavior is consistent with VMX, where CD/NW are not touched by vmentry/vmexit. Note that buggy firmware that does not clear CD/NW is _seriously_ old: SeaBIOS for example has been doing it since October 2008. Reviewed-by: Xiao Guangrong guangrong.x...@linux.intel.com

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/09/2015 11:18 PM, Paolo Bonzini wrote: On 09/07/2015 04:30, Xiao Guangrong wrote: diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 602b974a60a6..0f125c1860ec 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1085,6 +1085,47 @@ static u64 svm_compute_tsc_offset

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/07/2015 09:45 PM, Paolo Bonzini wrote: Right now, NPT page attributes are not used, and the final page attribute depends solely on gPAT (which however is not synced correctly), the guest MTRRs and the guest page attributes. However, we can do better by mimicking what is done for VMX. In

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/08/2015 07:19 PM, Paolo Bonzini wrote: On 08/07/2015 07:59, Xiao Guangrong wrote: On 07/07/2015 09:45 PM, Paolo Bonzini wrote: Right now, NPT page attributes are not used, and the final page attribute depends solely on gPAT (which however is not synced correctly), the guest MTRRs

Re: [PATCH 00/16] implement vNVDIMM

On 07/02/2015 02:17 PM, Michael S. Tsirkin wrote: On Wed, Jul 01, 2015 at 10:50:16PM +0800, Xiao Guangrong wrote: hw/acpi/aml-build.c | 32 +- hw/i386/acpi-build.c|9 +- hw/i386/acpi-dsdt.dsl |2 +- hw/i386/pc.c| 11 +- hw/mem

Re: [Qemu-devel] [PATCH 00/16] implement vNVDIMM

Thanks for your review, Stefan and Paolo! On 07/02/2015 05:52 PM, Paolo Bonzini wrote: On 02/07/2015 11:20, Stefan Hajnoczi wrote: Currently, the NVDIMM driver has been merged into upstream Linux Kernel and this patchset tries to enable it in virtualization field From a device model

Re: [Qemu-devel] [PATCH 14/16] nvdimm: support NFIT_CMD_GET_CONFIG_SIZE function

On 07/02/2015 05:23 PM, Stefan Hajnoczi wrote: On Wed, Jul 01, 2015 at 10:50:30PM +0800, Xiao Guangrong wrote: +static uint32_t dsm_cmd_config_size(struct dsm_buffer *in, struct dsm_out *out) +{ +GSList *list = get_nvdimm_built_list(); +PCNVDIMMDevice *nvdimm

[PATCH 13/16] nvdimm: support NFIT_CMD_IMPLEMENTED function

currently only allow to access device's Label Namespace Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/pc-nvdimm.c | 126 + 1 file changed, 126 insertions(+) diff --git a/hw/mem/pc-nvdimm.c b/hw/mem/pc-nvdimm.c index c0965ae

[PATCH 03/16] acpi: add aml_derefof

Implement DeRefOf term which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 8 include/hw/acpi/aml-build.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml

[PATCH 09/16] nvdimm: build ACPI NFIT table

are not needed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/acpi-build.c | 3 + hw/mem/pc-nvdimm.c | 286 + include/hw/mem/pc-nvdimm.h | 8 ++ 3 files changed, 297 insertions(+) diff --git a/hw/i386/acpi-build.c

[PATCH 00/16] implement vNVDIMM

/dev/pmem1 appears == TODO == 1) NVDIMM NUMA support 2) NVDIMM hotplug support Xiao Guangrong (16): acpi: allow aml_operation_region() working on 64 bit offset i386/acpi-build: allow SSDT to operate on 64 bit acpi: add aml_derefof acpi: add aml_sizeof acpi: add aml_create_field

[PATCH 08/16] nvdimm: init backend memory mapping and config data area

- the raw PMEM device on host, e,g /dev/pmem0 Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem/pc-nvdimm.c | 102 - include/hw/mem/pc-nvdimm.h | 5 +++ 2 files changed, 106 insertions(+), 1 deletion(-) diff --git a/hw

[PATCH 06/16] pc: implement NVDIMM device abstract

Introduce pc-nvdimm device and it only has one parameter, @file, which is the backed memory file for NVDIMM device We can use -device pc-nvdimm,file=/dev/pmem in the Qemu command to create NVDIMM device for the guest Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/mem

[PATCH 02/16] i386/acpi-build: allow SSDT to operate on 64 bit

allocate free space within this region which is used by NVDIMM _DSM method Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/i386/acpi-build.c | 4 ++-- hw/i386/acpi-dsdt.dsl | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi

[PATCH 05/16] acpi: add aml_create_field

Implement CreateField term which are used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 14 ++ include/hw/acpi/aml-build.h | 1 + 2 files changed, 15 insertions(+) diff --git a/hw/acpi/aml-build.c

[PATCH 04/16] acpi: add aml_sizeof

Implement SizeOf term which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 8 include/hw/acpi/aml-build.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml

[PATCH 01/16] acpi: allow aml_operation_region() working on 64 bit offset

Currently, the offset in OperationRegion is limited to 32 bit, extend it to 64 bit so that we can switch SSDT to 64 bit in later patch Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- hw/acpi/aml-build.c | 2 +- include/hw/acpi/aml-build.h | 2 +- 2 files changed, 2

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