Re: [PATCH 0/6] irqchip: GICv2/v3: Add support for irq_vcpu_affinity

2015-08-12 Thread Marc Zyngier
On 11/08/15 11:06, Eric Auger wrote:
 Hi Marc,
 
 The series works fine with KVM platform device passthrough use case
 (Calxeda Midway, GICv2, SPI assignment with VFIO). My integration branch
 can be found at
 https://git.linaro.org/people/eric.auger/linux.git/shortlog/refs/heads/v4.2-rc6-irq-forward-v3
 if useful.
 
 Tested-by: Eric Auger eric.au...@linaro.org

Many thanks for trying it (and for the review). I'll post an updated
version soon.

Thanks,

M.
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Re: [PATCH 0/6] irqchip: GICv2/v3: Add support for irq_vcpu_affinity

2015-08-11 Thread Eric Auger
Hi Marc,

The series works fine with KVM platform device passthrough use case
(Calxeda Midway, GICv2, SPI assignment with VFIO). My integration branch
can be found at
https://git.linaro.org/people/eric.auger/linux.git/shortlog/refs/heads/v4.2-rc6-irq-forward-v3
if useful.

Tested-by: Eric Auger eric.au...@linaro.org

Best Regards

Eric
On 07/09/2015 03:19 PM, Marc Zyngier wrote:
 The GICv2 and GICv3 architectures allow an active physical interrupt
 to be forwarded to a guest, and the guest to indirectly perform the
 deactivation of the interrupt by performing an EOI on the virtual
 interrupt (see for example the GICv2 spec, 3.2.1).
 
 This allows some substantial performance improvement for level
 triggered interrupts that otherwise have to be masked/unmasked in
 VFIO, not to mention the required trap back to KVM when the guest
 performs an EOI.
 
 To enable this, the GICs need to be switched to a different EOImode,
 where a taken interrupt can be left active (which prevents the same
 interrupt from being taken again), while other interrupts are still
 being processed normally.
 
 We also use the new irq_set_vcpu_affinity hook that was introduced for
 Intel's Posted Interrupts to determine whether or not to perform the
 deactivation at EOI-time.
 
 As all of this only makes sense when the kernel can behave as a
 hypervisor, we only enable this mode on detecting that the kernel was
 actually booted in HYP mode, and that the GIC supports this feature.
 
 This series is a complete rework of a RFC I sent over a year ago:
 
 http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266328.html
 
 Since then, a lot has been either merged (the irqchip_state) or reworked
 (my active-timer series: http://www.spinics.net/lists/kvm/msg118768.html),
 and this implements the last few bits for Eric Auger's series to
 finally make it into the kernel:
 
 https://lkml.org/lkml/2015/7/2/268
 https://lkml.org/lkml/2015/7/6/291
 
 With all these patches combined, physical interrupt routing from the
 kernel into a VM becomes possible.
 
 This has been tested on Juno (GICv2) and FastModel (GICv3). A branch
 is available at:
 
 git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git 
 irq/gic-irq-vcpu-affinity
 
 Marc Zyngier (6):
   irqchip: GICv3: Convert to EOImode == 1
   irqchip: GIC: Convert to EOImode == 1
   irqchip: GICv3: Skip LPI deactivation
   irqchip: GIC: Use chip_data instead of handler_data for cascaded
 interrupts
   irqchip: GICv3: Don't deactivate interrupts forwarded to a guest
   irqchip: GIC: Don't deactivate interrupts forwarded to a guest
 
  drivers/irqchip/irq-gic-v3.c   | 57 +++--
  drivers/irqchip/irq-gic.c  | 64 
 +++---
  include/linux/irqchip/arm-gic-v3.h |  9 ++
  include/linux/irqchip/arm-gic.h|  4 +++
  4 files changed, 126 insertions(+), 8 deletions(-)
 

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[PATCH 0/6] irqchip: GICv2/v3: Add support for irq_vcpu_affinity

2015-07-09 Thread Marc Zyngier
The GICv2 and GICv3 architectures allow an active physical interrupt
to be forwarded to a guest, and the guest to indirectly perform the
deactivation of the interrupt by performing an EOI on the virtual
interrupt (see for example the GICv2 spec, 3.2.1).

This allows some substantial performance improvement for level
triggered interrupts that otherwise have to be masked/unmasked in
VFIO, not to mention the required trap back to KVM when the guest
performs an EOI.

To enable this, the GICs need to be switched to a different EOImode,
where a taken interrupt can be left active (which prevents the same
interrupt from being taken again), while other interrupts are still
being processed normally.

We also use the new irq_set_vcpu_affinity hook that was introduced for
Intel's Posted Interrupts to determine whether or not to perform the
deactivation at EOI-time.

As all of this only makes sense when the kernel can behave as a
hypervisor, we only enable this mode on detecting that the kernel was
actually booted in HYP mode, and that the GIC supports this feature.

This series is a complete rework of a RFC I sent over a year ago:

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266328.html

Since then, a lot has been either merged (the irqchip_state) or reworked
(my active-timer series: http://www.spinics.net/lists/kvm/msg118768.html),
and this implements the last few bits for Eric Auger's series to
finally make it into the kernel:

https://lkml.org/lkml/2015/7/2/268
https://lkml.org/lkml/2015/7/6/291

With all these patches combined, physical interrupt routing from the
kernel into a VM becomes possible.

This has been tested on Juno (GICv2) and FastModel (GICv3). A branch
is available at:

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git 
irq/gic-irq-vcpu-affinity

Marc Zyngier (6):
  irqchip: GICv3: Convert to EOImode == 1
  irqchip: GIC: Convert to EOImode == 1
  irqchip: GICv3: Skip LPI deactivation
  irqchip: GIC: Use chip_data instead of handler_data for cascaded
interrupts
  irqchip: GICv3: Don't deactivate interrupts forwarded to a guest
  irqchip: GIC: Don't deactivate interrupts forwarded to a guest

 drivers/irqchip/irq-gic-v3.c   | 57 +++--
 drivers/irqchip/irq-gic.c  | 64 +++---
 include/linux/irqchip/arm-gic-v3.h |  9 ++
 include/linux/irqchip/arm-gic.h|  4 +++
 4 files changed, 126 insertions(+), 8 deletions(-)

-- 
2.1.4

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