On Thu, Jul 03, 2014 at 05:52:37PM +0200, Andi Kleen wrote:
If there's active LBR users out there, we should refuse to enable PT
and vice versa.
This doesn't work, e.g. hardware debuggers can take over at any time.
Tough cookies. Hardware debuggers get to deal with whatever crap
On Mon, Jul 07, 2014 at 05:46:35PM +0200, Peter Zijlstra wrote:
On Mon, Jul 07, 2014 at 01:57:16PM +, Liang, Kan wrote:
This doesn't work, e.g. hardware debuggers can take over at any time.
Tough cookies. Hardware debuggers get to deal with whatever crap they
cause.
If so,
On Mon, Jul 07, 2014 at 01:57:16PM +, Liang, Kan wrote:
This doesn't work, e.g. hardware debuggers can take over at any time.
Tough cookies. Hardware debuggers get to deal with whatever crap they
cause.
If so, I think I may discard this patch (2/3). I will resubmit the
other two
On Wed, Jul 02, 2014 at 11:14:14AM -0700, kan.li...@intel.com wrote:
From: Kan Liang kan.li...@intel.com
If RTIT_CTL.TraceEn=1, any attempt to read or write the LBR or LER MSRs,
including LBR_TOS, will result in a #GP.
Since Intel PT can be enabled/disabled at runtime, LBR MSRs have to be
If there's active LBR users out there, we should refuse to enable PT and
vice versa.
This doesn't work, e.g. hardware debuggers can take over at any time.
-Andi
--
a...@linux.intel.com -- Speaking for myself only.
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On Thu, Jul 03, 2014 at 05:52:37PM +0200, Andi Kleen wrote:
If there's active LBR users out there, we should refuse to enable PT and
vice versa.
This doesn't work, e.g. hardware debuggers can take over at any time.
Tough cookies. Hardware debuggers get to deal with whatever crap they
From: Kan Liang kan.li...@intel.com
If RTIT_CTL.TraceEn=1, any attempt to read or write the LBR or LER MSRs,
including LBR_TOS, will result in a #GP.
Since Intel PT can be enabled/disabled at runtime, LBR MSRs have to be
protected by _safe() at runtime.
Signed-off-by: Kan Liang
On Wed, Jul 02, 2014 at 11:14:14AM -0700, kan.li...@intel.com wrote:
From: Kan Liang kan.li...@intel.com
If RTIT_CTL.TraceEn=1, any attempt to read or write the LBR or LER MSRs,
including LBR_TOS, will result in a #GP.
Since Intel PT can be enabled/disabled at runtime, LBR MSRs have to be
