On Tue, Oct 02, 2012 at 08:45:54PM +0100, Peter Maydell wrote:
On 2 October 2012 20:28, Will Deacon will.dea...@arm.com wrote:
On Tue, Oct 02, 2012 at 07:31:43PM +0100, Peter Maydell wrote:
We probably want to be passing in the base of the cpu-internal
peripherals, rather than base of the
On Wed, Oct 3, 2012 at 6:02 AM, Will Deacon will.dea...@arm.com wrote:
On Tue, Oct 02, 2012 at 08:45:54PM +0100, Peter Maydell wrote:
On 2 October 2012 20:28, Will Deacon will.dea...@arm.com wrote:
On Tue, Oct 02, 2012 at 07:31:43PM +0100, Peter Maydell wrote:
We probably want to be passing
On Mon, Oct 01, 2012 at 10:14:26AM +0100, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
Add the init code for the hypervisor, the virtual machine, and
the virtual CPUs.
An interrupt handler is also wired to allow the VGIC maintenance
interrupts, used to deal with level
On Tue, 2 Oct 2012 10:24:13 +0100, Will Deacon will.dea...@arm.com
wrote:
On Mon, Oct 01, 2012 at 10:14:26AM +0100, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
Add the init code for the hypervisor, the virtual machine, and
the virtual CPUs.
An interrupt handler is also
On Oct 2, 2012, at 6:25 AM, Marc Zyngier marc.zyng...@arm.com wrote:
On Tue, 2 Oct 2012 10:24:13 +0100, Will Deacon will.dea...@arm.com
wrote:
On Mon, Oct 01, 2012 at 10:14:26AM +0100, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
Add the init code for the hypervisor,
On 2 October 2012 18:55, Christoffer Dall c.d...@virtualopensystems.com wrote:
On Oct 2, 2012, at 6:25 AM, Marc Zyngier marc.zyng...@arm.com wrote:
On Tue, 2 Oct 2012 10:24:13 +0100, Will Deacon will.dea...@arm.com
We really don't want the physical memory map for the guest hardwired in
the
On Tue, Oct 02, 2012 at 07:31:43PM +0100, Peter Maydell wrote:
We probably want to be passing in the base of the cpu-internal
peripherals, rather than base of the GIC specifically. For the
A15 these are the same thing, but that's not inherent [compare the
A9 which has more devices at fixed
On 2 October 2012 20:28, Will Deacon will.dea...@arm.com wrote:
On Tue, Oct 02, 2012 at 07:31:43PM +0100, Peter Maydell wrote:
We probably want to be passing in the base of the cpu-internal
peripherals, rather than base of the GIC specifically. For the
A15 these are the same thing, but that's
From: Marc Zyngier marc.zyng...@arm.com
Add the init code for the hypervisor, the virtual machine, and
the virtual CPUs.
An interrupt handler is also wired to allow the VGIC maintenance
interrupts, used to deal with level triggered interrupts and LR
underflows.
Signed-off-by: Marc Zyngier
