Avi,
On Tue, Mar 27, 2007 at 07:10:58PM +0200, Avi Kivity wrote:
The Performance counters (PMU) cannot be fully virtualized, they need to
run on the actual MSR registers. The PMU interrupt is controlled by the
local APIC. To get overflow-based sampling to work in a guest, we need to
Hi Avi,
Shobha Ranganathan wrote:
I am trying to capture in vmx.c the hardware
performance counter(PMU) interrupt of a i386 Linux
kernel running with perfmon on a Core 2 Duo machine
running with kvm-15. host is running kvm with VT-x in
x86-64 mode.
The PMU interrupt is programmed
Shobha Ranganathan wrote:
I am trying to capture in vmx.c the hardware
performance counter(PMU) interrupt of a i386 Linux
kernel running with perfmon on a Core 2 Duo machine
running with kvm-15. host is running kvm with VT-x in
x86-64 mode.
The PMU interrupt is programmed in the APIC LVT
I am trying to capture in vmx.c the hardware
performance counter(PMU) interrupt of a i386 Linux
kernel running with perfmon on a Core 2 Duo machine
running with kvm-15. host is running kvm with VT-x in
x86-64 mode.
The PMU interrupt is programmed in the APIC LVT entry
(set to 0xee)by the guest
I am trying to capture in vmx.c the hardware
performance counter(PMU) interrupt of a i386 Linux
kernel running with perfmon on a Core 2 Duo machine
running with kvm-15. host is running kvm with VT-x in
x86-64 mode.
The PMU interrupt is programmed in the APIC LVT entry
(set to 0xee)by the guest
