There is nothing in the code for emulating TCE tables in the kernel
that prevents it from working on "PR" KVM... other than ifdef's and
location of the code.
This renames book3s_64_vio_hv.c to book3s_64_vio.c and moves the
bulk of the code there.
This speeds things up a bit on my G5.
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arch/p
There's always a chance we're unable to read a guest instruction. The guest
could have its TLB mapped execute-, but not readable, something odd happens
and our TLB gets flushed. So it's a good idea to be prepared for that case
and have a fallback that allows us to fix things up in that case.
Add f
On 07.03.2012, at 18:08, Scott Wood wrote:
> On 03/07/2012 07:56 AM, Alexander Graf wrote:
>> On 03/01/2012 02:20 AM, Olivia Yin wrote:
>>> From: Liu Yu
>>>
>>> So that we can call it when improving SPE switch like book3e did for
>>> fp switch.
>>
>> Timur / Scott, can you please (n)ack this on
On PPC, CR2-CR4 are nonvolatile, thus have to be saved across function calls.
We didn't respect that for any architecture until Paul spotted it in his
patch for Book3S-HV. This patch saves/restores CR for all KVM capable PPC hosts.
Signed-off-by: Alexander Graf
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v1 -> v2:
- optimize booke
