[PATCH 1/2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Bharat Bhushan
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- arch/powerpc/kvm/e500.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h index c2e5e98..277cb18 100644 --- a/arch/powerpc/kvm/e500.h +++

[PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bharat Bhushan
If there is a struct page for the requested mapping then it's normal DDR and the mapping sets M bit (coherent, cacheable) else this is treated as I/O and we set I + G (cache inhibited, guarded) This helps setting proper TLB mapping for direct assigned device Signed-off-by: Bharat Bhushan

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 02:04 PM, Bharat Bhushan wrote: If there is a struct page for the requested mapping then it's normal DDR and the mapping sets M bit (coherent, cacheable) else this is treated as I/O and we set I + G (cache inhibited, guarded) This helps setting proper TLB mapping for direct

RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: “tiejun.chen” [mailto:tiejun.c...@windriver.com] Sent: Thursday, July 18, 2013 11:56 AM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421; Bhushan Bharat-R65777 Subject: Re: [PATCH 2/2] kvm:

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 03:12 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: “tiejun.chen” [mailto:tiejun.c...@windriver.com] Sent: Thursday, July 18, 2013 11:56 AM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421; Bhushan

RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of “tiejun.chen” Sent: Thursday, July 18, 2013 1:01 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421 Subject:

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 04:08 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of “tiejun.chen” Sent: Thursday, July 18, 2013 1:01 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org;

RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: “tiejun.chen” [mailto:tiejun.c...@windriver.com] Sent: Thursday, July 18, 2013 1:52 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421 Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 02:04 PM, Bharat Bhushan wrote: If there is a struct page for the requested mapping then it's normal DDR and the mapping sets M bit (coherent, cacheable) else this is treated as I/O and we set I + G (cache inhibited, guarded) This helps setting proper TLB mapping for direct

RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '“tiejun.chen”' Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421 Subject: RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '“tiejun.chen”' Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421 Subject: RE: [PATCH 2/2] kvm: powerpc: set

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 10:55, “tiejun.chen” wrote: On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '“tiejun.chen”' Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '“tiejun.chen”' Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott- B07421 Subject: RE: [PATCH 2/2] kvm:

RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Alexander Graf Sent: Thursday, July 18, 2013 3:19 PM To: Bhushan Bharat-R65777 Cc: “tiejun.chen”; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Wood Scott- B07421

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 05:44 PM, Alexander Graf wrote: On 18.07.2013, at 10:55, �tiejun.chen� wrote: On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '�tiejun.chen�' Cc: kvm-ppc@vger.kernel.org;

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 11:56, “tiejun.chen” wrote: On 07/18/2013 05:44 PM, Alexander Graf wrote: On 18.07.2013, at 10:55, �tiejun.chen� wrote: On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 12:08, “tiejun.chen” wrote: On 07/18/2013 05:48 PM, Alexander Graf wrote: On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM To: '�tiejun.chen�' Cc:

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 06:00 PM, Alexander Graf wrote: On 18.07.2013, at 11:56, “tiejun.chen” wrote: On 07/18/2013 05:44 PM, Alexander Graf wrote: On 18.07.2013, at 10:55, �tiejun.chen� wrote: On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread “tiejun.chen”
On 07/18/2013 06:12 PM, Alexander Graf wrote: On 18.07.2013, at 12:08, “tiejun.chen” wrote: On 07/18/2013 05:48 PM, Alexander Graf wrote: On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote: -Original Message- From: Bhushan Bharat-R65777 Sent: Thursday, July 18, 2013 1:53 PM

[PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Bharat Bhushan
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- v2: - No change arch/powerpc/kvm/e500.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h index c2e5e98..277cb18 100644 --- a/arch/powerpc/kvm/e500.h +++

[PATCH 2/2 v2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Bharat Bhushan
If there is a struct page for the requested mapping then it's normal RAM and the mapping is set to M bit (coherent, cacheable) otherwise this is treated as I/O and we set I + G (cache inhibited, guarded) This helps setting proper TLB mapping for direct assigned device Signed-off-by: Bharat

Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Alexander Graf
This needs a description. Why shouldn't we ignore E? Alex On 18.07.2013, at 15:19, Bharat Bhushan wrote: Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- v2: - No change arch/powerpc/kvm/e500.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git

Re: [PATCH 2/2 v2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 15:19, Bharat Bhushan wrote: If there is a struct page for the requested mapping then it's normal RAM and the mapping is set to M bit (coherent, cacheable) otherwise this is treated as I/O and we set I + G (cache inhibited, guarded) This helps setting proper TLB

Re: [PATCH 2/2 v2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 17:15, Bhushan Bharat-R65777 wrote: -Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Alexander Graf Sent: Thursday, July 18, 2013 8:23 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org;

Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 17:12, Bhushan Bharat-R65777 wrote: -Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Alexander Graf Sent: Thursday, July 18, 2013 8:18 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org;

RE: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Bhushan Bharat-R65777
-Original Message- From: Alexander Graf [mailto:ag...@suse.de] Sent: Thursday, July 18, 2013 8:50 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Wood Scott-B07421 Subject: Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2 On

Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Scott Wood
On 07/18/2013 05:00:42 AM, Alexander Graf wrote: Now why is setting invalid flags a problem? If I understand Scott correctly, it can break the host if you access certain host devices with caching enabled. But to be sure I'd say we ask him directly :). The architecture makes it illegal to

Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2

2013-07-18 Thread Scott Wood
On 07/18/2013 10:12:30 AM, Bhushan Bharat-R65777 wrote: -Original Message- From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Alexander Graf Sent: Thursday, July 18, 2013 8:18 PM To: Bhushan Bharat-R65777 Cc: kvm-ppc@vger.kernel.org;

Re: [PATCH 2/2 v2] kvm: powerpc: set cache coherency only for kernel managed pages

2013-07-18 Thread Alexander Graf
On 18.07.2013, at 19:17, Scott Wood wrote: On 07/18/2013 08:19:03 AM, Bharat Bhushan wrote: If there is a struct page for the requested mapping then it's normal RAM and the mapping is set to M bit (coherent, cacheable) otherwise this is treated as I/O and we set I + G (cache inhibited,

Re: [PATCH 00/10 v6] KVM: PPC: IOMMU in-kernel handling

2013-07-18 Thread Alexey Kardashevskiy
On 07/16/2013 10:53 AM, Alexey Kardashevskiy wrote: The changes are: 1. rebased on v3.11-rc1 so the capability numbers changed again 2. fixed multiple comments from maintainers 3. KVM: PPC: Add support for IOMMU in-kernel handling is split into 2 patches, the new one is powerpc/iommu: rework