changes since v3:
- use kvmppc namespace
- MPP_BUFFER_ORDER of 3 not 4, as we only need 32k and it's already 32k aligned
- split out kvmppc_vcore_create in separate patch
- give a variable a better name: s/tmp/mpp_addr/
- logmpp becomes static inline function
Stewart Smith (2):
Split out struct
No code changes, just split it out to a function so that with the addition
of micro partition prefetch buffer allocation (in subsequent patch) looks
neater and doesn't require excessive indentation.
Signed-off-by: Stewart Smith
---
arch/powerpc/kvm/book3s_hv.c | 31 +---
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start restore by writing
to a SPR.
The logmpp ins
Alexander Graf writes:
>> diff --git a/arch/powerpc/include/asm/kvm_host.h
>> b/arch/powerpc/include/asm/kvm_host.h
>> index 1eaea2d..5769497 100644
>> --- a/arch/powerpc/include/asm/kvm_host.h
>> +++ b/arch/powerpc/include/asm/kvm_host.h
>> @@ -305,6 +305,8 @@ struct kvmppc_vcore {
>> u32 a
Paul Mackerras writes:
> On Thu, Jul 17, 2014 at 01:19:57PM +1000, Stewart Smith wrote:
>
>> The POWER8 processor has a Micro Partition Prefetch Engine, which is
>> a fancy way of saying "has way to store and load contents of L2 or
>> L2+MRU way of L3 cache". We initiate the storing of the log (li
On Thu, 2014-07-17 at 17:01 +0530, Bharat Bhushan wrote:
> There are shadow registers like, GSPRG[0-3], GSRR0, GSRR1 etc on
> BOOKE-HV and these shadow registers are guest accessible.
> So these shadow registers needs to be updated on BOOKE-HV.
> This patch adds new macro for get/set helper of shad
On Fri, 2014-07-18 at 02:37 +0200, Alexander Graf wrote:
> On 18.07.14 02:36, Scott Wood wrote:
> > On Fri, 2014-07-18 at 02:33 +0200, Alexander Graf wrote:
> >> On 18.07.14 02:28, Scott Wood wrote:
> >>> On Thu, 2014-07-17 at 18:29 +0200, Alexander Graf wrote:
> On 17.07.14 18:27, Alexander G
On 18.07.14 02:36, Scott Wood wrote:
On Fri, 2014-07-18 at 02:33 +0200, Alexander Graf wrote:
On 18.07.14 02:28, Scott Wood wrote:
On Thu, 2014-07-17 at 18:29 +0200, Alexander Graf wrote:
On 17.07.14 18:27, Alexander Graf wrote:
On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
-Or
On Fri, 2014-07-18 at 02:33 +0200, Alexander Graf wrote:
> On 18.07.14 02:28, Scott Wood wrote:
> > On Thu, 2014-07-17 at 18:29 +0200, Alexander Graf wrote:
> >> On 17.07.14 18:27, Alexander Graf wrote:
> >>> On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
> > -Original Message-
On 18.07.14 02:28, Scott Wood wrote:
On Thu, 2014-07-17 at 18:29 +0200, Alexander Graf wrote:
On 17.07.14 18:27, Alexander Graf wrote:
On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 17, 2014 9:
On Thu, 2014-07-17 at 18:29 +0200, Alexander Graf wrote:
> On 17.07.14 18:27, Alexander Graf wrote:
> >
> > On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
> >>
> >>> -Original Message-
> >>> From: Alexander Graf [mailto:ag...@suse.de]
> >>> Sent: Thursday, July 17, 2014 9:41 PM
> >>
On Thu, Jul 17, 2014 at 01:19:57PM +1000, Stewart Smith wrote:
> The POWER8 processor has a Micro Partition Prefetch Engine, which is
> a fancy way of saying "has way to store and load contents of L2 or
> L2+MRU way of L3 cache". We initiate the storing of the log (list of
> addresses) using the l
On Thu, 17 Jul 2014 11:36:07 +0200 Marek Szyprowski
wrote:
> MAX_CMA_AREAS is used by other subsystems (i.e. arch/arm/mm/dma-mapping.c),
> so we need to provide correct definition even if CMA is disabled.
> This patch fixes this issue.
>
> Reported-by: Sylwester Nawrocki
> Signed-off-by: Marek
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 17, 2014 9:58 PM
> To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
> Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [PATCH] kvm: ppc: booke: Restore SPRG3 when ent
On 17.07.14 18:27, Alexander Graf wrote:
On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 17, 2014 9:41 PM
To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
Cc: k...@vger.kernel.org; Wood Scott
On 17.07.14 18:24, bharat.bhus...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 17, 2014 9:41 PM
To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248
Subject: Re: [
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 17, 2014 9:41 PM
> To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
> Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [PATCH] kvm: ppc: booke: Restore SPRG3 when ent
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 17, 2014 9:47 PM
> To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
> Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [PATCH] kvm: ppc: bookehv: Save restore SPRN_SP
On 16.07.14 07:49, Bharat Bhushan wrote:
SPRN_SPRG is used by debug interrupt handler, so this is required
for debug support.
Signed-off-by: Bharat Bhushan
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kernel/asm-offsets.c | 1 +
arch/powerpc/kvm/bookehv_interrupts.S |
On 16.07.14 08:02, Bharat Bhushan wrote:
SPRG3 is guest accessible and SPRG3 can be clobbered by host
or another guest, So this need to be restored when loading
guest state.
Signed-off-by: Bharat Bhushan
---
arch/powerpc/kvm/booke_interrupts.S | 2 ++
1 file changed, 2 insertions(+)
diff -
On 17.07.14 13:22, Mihai Caraman wrote:
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infi
On 17.07.14 13:22, Mihai Caraman wrote:
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution t
On 17.07.14 13:22, Mihai Caraman wrote:
In the context of replacing kvmppc_ld() function calls with a version of
kvmppc_get_last_inst() which allow to fail, Alex Graf suggested this:
"If we get EMULATE_AGAIN, we just have to make sure we go back into the guest.
No need to inject an ISI into th
> -Original Message-
> From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-
> ow...@vger.kernel.org] On Behalf Of Bharat Bhushan
> Sent: Thursday, July 17, 2014 2:32 PM
> To: ag...@suse.de; kvm-ppc@vger.kernel.org
> Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248; Bhushan
>
On 17.07.14 13:31, Bharat Bhushan wrote:
These are primarily the cleanup patches, where shared struct get/set
helper function are enhanced to handle shadow registers and uses those
helper functions.
Eventually this also fix SRR0/1 synchronization from userspace
v1->v2
- Compilation fix for bo
On 17.07.14 13:31, Bharat Bhushan wrote:
kvmppc_set_epr() is already defined in asm/kvm_ppc.h, So
rename and move get_epr helper function to same file.
Signed-off-by: Bharat Bhushan
---
v1->v2
- vcpu->arch.epr under CONFIG_BOOKE
arch/powerpc/include/asm/kvm_ppc.h | 10 ++
arch/po
kvmppc_set_epr() is already defined in asm/kvm_ppc.h, So
rename and move get_epr helper function to same file.
Signed-off-by: Bharat Bhushan
---
v1->v2
- vcpu->arch.epr under CONFIG_BOOKE
arch/powerpc/include/asm/kvm_ppc.h | 10 ++
arch/powerpc/kvm/booke.c | 11 +--
2
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman
---
v5-v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/inc
Use kvmppc_set_sprg[0-7]() and kvmppc_get_sprg[0-7]() helper
functions
Signed-off-by: Bharat Bhushan
---
arch/powerpc/kvm/booke.c | 32
arch/powerpc/kvm/booke_emulate.c | 8
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/p
Add and use kvmppc_set_esr() and kvmppc_get_esr() helper functions
Signed-off-by: Bharat Bhushan
---
arch/powerpc/include/asm/kvm_ppc.h | 1 +
arch/powerpc/kvm/booke.c | 24 +++-
2 files changed, 4 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/include/a
There are shadow registers like, GSPRG[0-3], GSRR0, GSRR1 etc on
BOOKE-HV and these shadow registers are guest accessible.
So these shadow registers needs to be updated on BOOKE-HV.
This patch adds new macro for get/set helper of shadow register .
Signed-off-by: Bharat Bhushan
---
v1->v2
- Fix c
Uses kvmppc_set_dar() and kvmppc_get_dar() helper functions
Signed-off-by: Bharat Bhushan
---
arch/powerpc/kvm/booke.c | 24 +++-
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 096998a..20296c8 100644
-
Use kvmppc_set_srr0/srr1() and kvmppc_get_srr0/srr1() helper functions
Signed-off-by: Bharat Bhushan
---
arch/powerpc/kvm/booke.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index c2471ed..096998a 1006
On book3e, KVM uses load external pid (lwepx) dedicated instruction to read
guest last instruction on the exit path. lwepx exceptions (DTLB_MISS, DSI
and LRAT), generated by loading a guest address, needs to be handled by KVM.
These exceptions are generated in a substituted guest translation contex
In the context of replacing kvmppc_ld() function calls with a version of
kvmppc_get_last_inst() which allow to fail, Alex Graf suggested this:
"If we get EMULATE_AGAIN, we just have to make sure we go back into the guest.
No need to inject an ISI into the guest - it'll do that all by itself.
With
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infinite loop caused by lwepx's data TLB miss
e
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution to read the guest
last instruction, by allow
The commit 1d628af7 "add load inst fixup" made an attempt to handle
failures generated by reading the guest current instruction. The fixup
code that was added works by chance hiding the real issue.
Load external pid (lwepx) instruction, used by KVM to read guest
instructions, is executed in a subs
MAX_CMA_AREAS is used by other subsystems (i.e. arch/arm/mm/dma-mapping.c),
so we need to provide correct definition even if CMA is disabled.
This patch fixes this issue.
Reported-by: Sylwester Nawrocki
Signed-off-by: Marek Szyprowski
---
include/linux/cma.h | 4
1 file changed, 4 insertio
Hello,
On 2014-06-16 07:40, Joonsoo Kim wrote:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
>From my guess, it is caused by some needs on
On 16.07.14 06:21, bharat.bhus...@freescale.com wrote:
-Original Message-
From: Caraman Mihai Claudiu-B02008
Sent: Tuesday, July 15, 2014 10:20 PM
To: Alexander Graf
Cc: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
Subject: Re: [PATCH 6/6] kvm: ppc: Add SPRN_SPR get helper function
On 17.07.14 05:19, Stewart Smith wrote:
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start r
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