[PULL 13/24] KVM: PPC: Make ONE_REG powerpc generic

From: Mihai Caraman mihai.cara...@freescale.com Make ONE_REG generic for server and embedded architectures by moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by: Alexander Graf

[PULL 21/24] KVM: PPC: Book3E: Enable e6500 core

From: Mihai Caraman mihai.cara...@freescale.com Now that AltiVec and hardware thread support is in place enable e6500 core. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by: Alexander Graf ag...@suse.de --- arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10

[PULL 16/24] KVM: PPC: Remove the tasklet used by the hrtimer

From: Mihai Caraman mihai.cara...@freescale.com Powerpc timer implementation is a copycat version of s390. Now that they removed the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this optimization. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by:

[PULL 11/24] KVM: PPC: Book3E: Increase FPU laziness

From: Mihai Caraman mihai.cara...@freescale.com Increase FPU laziness by loading the guest state into the unit before entering the guest instead of doing it on each vcpu schedule. Without this improvement an interrupt may claim floating point corrupting guest state. Signed-off-by: Mihai Caraman

[PULL 19/24] KVM: PPC: Book3S HV: Only accept host PVR value for guest PVR

From: Paul Mackerras pau...@samba.org Since the guest can read the machine's PVR (Processor Version Register) directly and see the real value, we should disallow userspace from setting any value for the guest's PVR other than the real host value. Therefore this makes kvm_arch_vcpu_set_sregs_hv()

[PULL 09/24] KVM: PPC: Book3S HV: Add register name when loading toc

From: Michael Neuling mi...@neuling.org Add 'r' to register name r2 in kvmppc_hv_enter. Also update comment at the top of kvmppc_hv_enter to indicate that R2/TOC is non-volatile. Signed-off-by: Michael Neuling mi...@neuling.org Signed-off-by: Paul Mackerras pau...@samba.org Signed-off-by:

[PULL 12/24] KVM: PPC: Book3e: Add AltiVec support

From: Mihai Caraman mihai.cara...@freescale.com Add AltiVec support in KVM for Book3e. FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Book3e specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2

[PULL 18/24] KVM: PPC: Book3S HV: Increase timeout for grabbing secondary threads

From: Paul Mackerras pau...@au1.ibm.com Occasional failures have been seen with split-core mode and migration where the message KVM: couldn't grab cpu appears. This increases the length of time that we wait from 1ms to 10ms, which seems to work around the issue. Signed-off-by: Paul Mackerras

[PULL 07/24] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

From: Mihai Caraman mihai.cara...@freescale.com SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and

[PULL 20/24] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

From: Mihai Caraman mihai.cara...@freescale.com ePAPR represents hardware threads as cpu node properties in device tree. So with existing QEMU, hardware threads are simply exposed as vcpus with one hardware thread. The e6500 core shares TLBs between hardware threads. Without tlb write

[PULL 10/24] KVM: PPC: BOOKE: Add one_reg documentation of SPRG9 and DBSR

From: Bharat Bhushan bharat.bhus...@freescale.com This was missed in respective one_reg implementation patch. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com Signed-off-by: Alexander Graf ag...@suse.de --- Documentation/virtual/kvm/api.txt | 2 ++ 1 file changed, 2 insertions(+)

[PULL 24/24] KVM: PPC: Pass enum to kvmppc_get_last_inst

The kvmppc_get_last_inst function recently received a facelift that allowed us to pass an enum of the type of instruction we want to read into it rather than an unreadable boolean. Unfortunately, not all callers ended up passing the enum. This wasn't really an issue as true and false happen to

[PULL 14/24] KVM: PPC: Move ONE_REG AltiVec support to powerpc

From: Mihai Caraman mihai.cara...@freescale.com Move ONE_REG AltiVec support to powerpc generic layer. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Signed-off-by: Alexander Graf ag...@suse.de --- arch/powerpc/include/uapi/asm/kvm.h | 5 + arch/powerpc/kvm/book3s.c |

[PULL 04/24] KVM: PPC: BOOKE: Clear guest dbsr in userspace exit KVM_EXIT_DEBUG

From: Bharat Bhushan bharat.bhus...@freescale.com Dbsr is not visible to userspace and we do not think any need to expose this to userspace because: Userspace cannot inject debug interrupt to guest (as this does not know guest ability to handle debug interrupt), so userspace will always

[PULL 06/24] KVM: PPC: BOOKE: Add one reg interface for DBSR

From: Bharat Bhushan bharat.bhus...@freescale.com Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com Signed-off-by: Alexander Graf ag...@suse.de --- arch/powerpc/include/uapi/asm/kvm.h | 1 + arch/powerpc/kvm/booke.c| 6 ++ 2 files changed, 7 insertions(+) diff --git

[PULL 01/24] KVM: PPC: BOOKE: allow debug interrupt at debug level

From: Bharat Bhushan bharat.bhus...@freescale.com Debug interrupt can be either critical level or debug level. There are separate set of save/restore registers used for different level. Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1 are used for critical level debug interrupt.

[PULL 08/24] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

From: Mihai Caraman mihai.cara...@freescale.com Book3E specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2 cores while AltiVec is present in e6500 core. So we can currently decide at compile-time which unit to support exclusively. As

[PULL 03/24] KVM: PPC: BOOKE: Allow guest to change MSR_DE

From: Bharat Bhushan bharat.bhus...@freescale.com This patch changes the default behavior of MSRP_DEP, that is guest is not allowed to change the MSR_DE, to guest can change MSR_DE. When userspace is debugging guest then it override the default behavior and set MSRP_DEP. This stops guest to

[PULL 00/24] ppc patch queue 2014-09-24

Hi Paolo, This is my current patch queue for ppc. Please pull. Alex The following changes since commit f51770ed465e6eb41da7fa16fd92eb67069600cf: kvm: Make init_rmode_identity_map() return 0 on success. (2014-09-17 13:10:12 +0200) are available in the git repository at:

[PULL 17/24] KVM: PPC: Remove shared defines for SPE and AltiVec interrupts

From: Mihai Caraman mihai.cara...@freescale.com We currently decide at compile-time which of the SPE or AltiVec units to support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and CONFIG_PPC_E500MC and remove shared defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com

[PULL 23/24] powerpc/kvm: common sw breakpoint instr across ppc

From: Madhavan Srinivasan ma...@linux.vnet.ibm.com This patch extends the use of illegal instruction as software breakpoint instruction across the ppc platform. Patch extends booke program interrupt code to support software breakpoint. Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com

[PULL 15/24] KVM: PPC: BOOKE: Emulate debug registers and exception

From: Bharat Bhushan bharat.bhus...@freescale.com This patch emulates debug registers and debug exception to support guest using debug resource. This enables running gdb/kgdb etc in guest. On BOOKE architecture we cannot share debug resources between QEMU and guest because: When QEMU is

Re: [PULL 00/24] ppc patch queue 2014-09-24

Il 24/09/2014 22:43, Alexander Graf ha scritto: Hi Paolo, This is my current patch queue for ppc. Please pull. Alex The following changes since commit f51770ed465e6eb41da7fa16fd92eb67069600cf: kvm: Make init_rmode_identity_map() return 0 on success. (2014-09-17 13:10:12 +0200)