On 26.05.15 02:14, Sam Bobroff wrote:
On Mon, May 25, 2015 at 11:08:08PM +0200, Alexander Graf wrote:
On 20.05.15 07:26, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed
On Mon, May 25, 2015 at 11:08:08PM +0200, Alexander Graf wrote:
On 20.05.15 07:26, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed as such.
This patch corrects
On Wed, May 20, 2015 at 03:26:12PM +1000, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed as such.
This patch corrects places where it is accessed as a 32 bit field by a
On Wed, 2015-05-20 at 15:26 +1000, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed as such.
This patch corrects places where it is accessed as a 32 bit field by a
64 bit
On Wed, May 20, 2015 at 05:35:08PM -0500, Scott Wood wrote:
It's nominally a 64-bit register, but the upper 32 bits are reserved in
ISA 2.06. Do newer ISAs or certain implementations define things in the
upper 32 bits, or is this just about the asm accesses being wrong on
big-endian?
It's
