[PATCH 0/7 v3] Guest debug emulation

This patchset adds debug register and interrupt emulation support for guest, which enables running gdb/kgdb etc in guest. v2-v3 - Added One-reg interface for DBSR - removed arch-shadow_dbg_reg - Addressed some more comments on v2 (detail in individual patch) Bharat Bhushan (7): KVM: PPC:

[PATCH 2/7 v3] KVM: PPC: BOOKE : Emulate rfdi instruction

This patch adds rfdi instruction emulation which is required for guest debug hander on BOOKE-HV Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- v2-v3 - No change arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/booke_emulate.c| 13 + 2 files changed,

[PATCH 1/7 v3] KVM: PPC: BOOKE: allow debug interrupt at debug level

Debug interrupt can be either critical level or debug level. There are separate set of save/restore registers used for different level. Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1 are used for critical level debug interrupt. Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt

[PATCH 4/7 v3] KVM: PPC: BOOKE: Clear guest dbsr in userspace exit KVM_EXIT_DEBUG

Dbsr is not visible to userspace and we do not think any need to expose this to userspace because: Userspace cannot inject debug interrupt to guest (as this does not know guest ability to handle debug interrupt), so userspace will always clear DBSR. Now if userspace has to always clear

[PATCH 7/7 v3] KVM: PPC: BOOKE: Emulate debug registers and exception

This patch emulates debug registers and debug exception to support guest using debug resource. This enables running gdb/kgdb etc in guest. On BOOKE architecture we cannot share debug resources between QEMU and guest because: When QEMU is using debug resources then debug exception must be

[PATCH 5/7 v3] KVM: PPC: BOOKE: Guest and hardware visible debug registers are same

Guest visible debug register and hardware visible debug registers are same, so ther is no need to have arch-shadow_dbg_reg, instead use arch-dbg_reg. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- v2-v3 - New Patch ( As per comment we are now using arch-dbg_reg only)

[PATCH 6/7 v3] KVM: PPC: BOOKE: Add one reg interface for DBSR

Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- v2-v3 - New patch arch/powerpc/include/uapi/asm/kvm.h | 1 + arch/powerpc/kvm/booke.c| 6 ++ 2 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h

[PATCH 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

Though SPE/AltiVec shares interrupts numbers on BookE cores, use distinct defines to identify these numbers. This improves code readability especially in KVM. Revert c58ce397 and 6b310fc5 patches that added common defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com ---

[PATCH 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai

Re: [PATCH 0/6] IRQFD without IRQ routing, enabled for XICS

Il 05/08/2014 14:27, Paolo Bonzini ha scritto: Il 30/06/2014 12:51, Paul Mackerras ha scritto: This series of patches provides a way to implement IRQFD support without having to implement IRQ routing, and adds IRQFD support for the XICS interrupt controller emulation. (XICS is the interrupt

[PATCH] KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core

ePAPR represents hardware threads as cpu node properties in device tree. So with existing QEMU, hardware threads are simply exposed as vcpus with one hardware thread. The e6500 core shares TLBs between hardware threads. Without tlb write conditional instruction, the Linux kernel uses per core