On 16.10.2012, at 21:33, Benjamin Herrenschmidt wrote:
On Tue, 2012-10-16 at 17:00 +1100, Michael Ellerman wrote:
Thanks for looking at this - but in fact this is fixed by my patch
entitled KVM: PPC: Book3S HV: Fix some races in starting secondary
threads submitted back on August 28.
OK
On 10/16/2012 10:03 PM, Anthony Liguori wrote:
This forces userspace to dedicate a thread for the HPT.
If no changes are available, does read return a size 0? I don't think
it's necessary to support polling. The kernel should always be able to
respond to userspace here. The only catch
On 10/16/2012 11:52 PM, Paul Mackerras wrote:
On Tue, Oct 16, 2012 at 03:06:33PM +0200, Avi Kivity wrote:
On 10/16/2012 01:58 PM, Paul Mackerras wrote:
On Tue, Oct 16, 2012 at 12:06:58PM +0200, Avi Kivity wrote:
Does/should the fd support O_NONBLOCK and poll? (=waiting for an entry
to
On 10/16/2012 04:49 PM, Alexander Graf wrote:
If there is a lot of prioritization and/or queuing logic, then yes. But
what about MSI? Doesn't that have a direct path?
Nope. Well, yes, in a certain special case where the MPIC pushes the
interrupt vector on interrupt delivery into a special
On 10/17/2012 04:50 PM, Avi Kivity wrote:
On 10/16/2012 04:49 PM, Alexander Graf wrote:
If there is a lot of prioritization and/or queuing logic, then yes. But
what about MSI? Doesn't that have a direct path?
Nope. Well, yes, in a certain special case where the MPIC pushes the
interrupt
On 10/14/2012 02:04 AM, Christoffer Dall wrote:
*** warning: this RFC patch series is only compile-tested ***
We need a way to specify the address at which we expect VMs to access
the interrupt controller (both the emulated distributor and the hardware
interface supporting virtualization).
On Wed, Oct 17, 2012 at 4:38 PM, Alexander Graf ag...@suse.de wrote:
On 10/14/2012 02:04 AM, Christoffer Dall wrote:
*** warning: this RFC patch series is only compile-tested ***
We need a way to specify the address at which we expect VMs to access
the interrupt controller (both the emulated
On Wed, 2012-10-17 at 16:39 -0400, Christoffer Dall wrote:
Have you talked to Ben about this one? He wanted to design a new, more
flexible irqchip API that would work for XICS MPIC. Maybe there's some
room for cooperation here?
I have not - Ben, what do you have in mind?
I've been
On Wed, Oct 17, 2012 at 04:39:57PM -0400, Christoffer Dall wrote:
On Wed, Oct 17, 2012 at 4:38 PM, Alexander Graf ag...@suse.de wrote:
On 10/14/2012 02:04 AM, Christoffer Dall wrote:
*** warning: this RFC patch series is only compile-tested ***
We need a way to specify the address at
On Thu, 2012-10-18 at 09:10 +1100, Paul Mackerras wrote:
With the XICS, there are two types of irqchip: a source controller and
a presentation controller. There is one presentation controller per
vcpu and typically one source controller per PCI host bridge (a source
controller can manage
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