Hi Liu,
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
When kvm is enabled on a core, we migrate all external irq to primary
thread. Since currently, the kvmirq logic is handled by the primary
hwthread.
Todo: this patch lacks re-enable of irqbalance when kvm is disable on
the core
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
(This patch is a place holder.)
If there is only one vcpu thread is ready(the other vcpu thread can
wait for it to execute), the primary thread can enter tickless mode,
We do not configure NOHZ_FULL to y by default. Hence no thread would
Hi Liu,
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
Nowadays, powerKVM runs with secondary hwthread offline. Although
we can make all secondary hwthread online later, we still preserve
this behavior for dedicated KVM env. Achieve this by setting
paca-online as false.
Signed-off-by:
Hi Liu,
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
To enter guest, primary hwtherad schedules the stopper func on
secondary threads and force them into NAP mode.
When exit to host,secondary threads hardcode to restore the stack,
then switch back to the stopper func, i.e host.
This patch series introduces dirty page logging for ARMv7 and adds some degree
of generic dirty logging support for x86, armv7 and later armv8.
I implemented Alex's suggestion after he took a look at the patches at kvm
forum to simplify the generic/arch split - leaving mips, powerpc, s390,
This patch defines KVM_GENERIC_DIRTYLOG, and moves dirty log read function
to it's own file virt/kvm/dirtylog.c. x86 is updated to use the generic
dirty log interface, selecting KVM_GENERIC_DIRTYLOG in its Kconfig and
makefile. No other architectures are affected, each uses it's own version.
This
This patch adds support for architecture implemented VM TLB flush, currently
ARMv7 defines HAVE_KVM_ARCH_TLB_FLUSH_ALL. This leaves other architectures
unaffected using the generic version. In subsequent patch ARMv7 defines
HAVE_KVM_ARCH_TLB_FLUSH_ALL and it's own TLB flush interface.
This patch adds ARMv7 architecture TLB Flush function.
Acked-by: Christoffer Dall christoffer.dall at linaro.org
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/include/asm/kvm_asm.h |1 +
arch/arm/include/asm/kvm_host.h | 12
arch/arm/kvm/Kconfig
Patch adds support for initial write protection of VM memlsot. This patch
series assumes that huge PUDs will not be used in 2nd stage tables, which is
awlays valid on ARMv7.
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/include/asm/kvm_host.h |2 +
This patch adds support for handling 2nd stage page faults during migration,
it disables faulting in huge pages, and dissolves huge pages to page tables.
In case migration is canceled huge pages are used again.
Reviewed-by: Christoffer Dall christoffer.dall at linaro.org
Signed-off-by: Mario
This patch adds support to track VM dirty pages, between dirty log reads. Pages
that have been dirtied since last log read are write protected again, in
preparation of next dirty log read. In addition ARMv7 dirty log read function
is pushed up to generic layer.
Signed-off-by: Mario Smarduch
In kvm_test_clear_dirty_npages(), if we find an invalid HPTE we move on to the
next HPTE without unlocking the invalid one. In fact we should never
find an invalid and unlocked HPTE in the rmap chain, but for robustness
we should unlock it. This adds the missing unlock.
Reported-by: Benjamin
Minor cleanup
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index
We switch to unlock variant with memory barriers in the error path
and also in code path where we had implicit dependency on previous
functions calling lwsync/ptesync. In most of the cases we don't really
need an explicit barrier, but using the variant make sure we don't make
mistakes later with
This patch adds helper routine for lock and unlock hpte and use
the same for rest of the code. We don't change any locking rules in this
patch. In the next patch we switch some of the unlock usage to use
the api with barrier and also document the usage without barriers.
Signed-off-by: Aneesh
To enter guest, primary hwtherad schedules the stopper func on
secondary threads and force them into NAP mode.
When exit to host,secondary threads hardcode to restore the stack,
then switch back to the stopper func, i.e host.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
(This is a place holder patch.)
We need to store the time base for host on secondary hwthread.
Later when switching back, we need to reprogram it with elapse
time.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 6 ++
1 file changed, 6
The proto will be:
cpu1 cpuX
stop_cpus_async()
bring cpuX to a special state
signal flag and trapped
check for flag
The func help powerpc to reuse the scheme of cpu_stopper_task
to force the
When kvm is enabled on a core, we migrate all external irq to primary
thread. Since currently, the kvmirq logic is handled by the primary
hwthread.
Todo: this patch lacks re-enable of irqbalance when kvm is disable on
the core
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
(This patch is a place holder.)
If there is only one vcpu thread is ready(the other vcpu thread can
wait for it to execute), the primary thread can enter tickless mode,
which causes the primary keeps running, so the secondary has no
opportunity to exit to host, even they have other tsk on them.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/kvm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 602eb51..de38566 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -93,6
Nowadays, powerKVM runs with secondary hwthread offline. Although
we can make all secondary hwthread online later, we still preserve
this behavior for dedicated KVM env. Achieve this by setting
paca-online as false.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
The secondary thread can only jump back to host until primary has set
up the env. Add host_ready field in kvm_vcore to sync this action.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kernel/asm-offsets.c | 3 +++
When vcpu thread runs at the first time, it will ensure to stick
to the primary thread.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kvm/book3s_hv.c| 17 +
2 files changed, 20 insertions(+)
diff
The primary hwthread ceases the scheduler of secondary hwthread by
bringing them into NAP. Then, the secondary is ready for guest.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_hv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
On Thu, Oct 02, 2014 at 07:06:40PM +0200, Alexander Graf wrote:
I think we're best off to keep the user space API native endian. So
really we should only ever have to convert from big to native endian on
read and native to big on write.
With that QEMU should do the right thing already, no?
Am 03.10.2014 um 14:05 schrieb Paul Mackerras pau...@samba.org:
On Thu, Oct 02, 2014 at 07:06:40PM +0200, Alexander Graf wrote:
I think we're best off to keep the user space API native endian. So
really we should only ever have to convert from big to native endian on
read and native to
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/04/2014 07:05 AM, Alexander Graf wrote:
Am 03.10.2014 um 14:05 schrieb Paul Mackerras pau...@samba.org:
On Thu, Oct 02, 2014 at 07:06:40PM +0200, Alexander Graf wrote:
I think we're best off to keep the user space API native endian.
Mac OS X boots with MoL/PR KVM on an AmigaONE X1000 PowerPC (YouTube
video): http://youtu.be/7alchoY6kzY
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To unsubscribe from this list: send the line unsubscribe kvm-ppc in
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More majordomo info at http://vger.kernel.org/majordomo-info.html
Saving and restoring guests on a KVM little endian host is currently
broken because qemu assumes that htabs are big endian.
This patch modifies kvm_htab_read and kvm_htab_write to make sure
that the endianness expected by qemu is enforced on big and little
endian hosts.
Signed-off-by: Cédric
On 02.10.14 18:58, Cédric Le Goater wrote:
Saving and restoring guests on a KVM little endian host is currently
broken because qemu assumes that htabs are big endian.
This patch modifies kvm_htab_read and kvm_htab_write to make sure
that the endianness expected by qemu is enforced on
On 29.09.14 10:02, Aneesh Kumar K.V wrote:
We use cma reserved area for creating guest hash page table.
Don't do the reservation in non-hypervisor mode. This avoids unnecessary
CMA reservation when booting with limited memory configs like
fadump and kdump.
Signed-off-by: Aneesh Kumar K.V
Il 29/09/2014 10:28, Alexander Graf ha scritto:
On 29.09.14 10:02, Aneesh Kumar K.V wrote:
We use cma reserved area for creating guest hash page table.
Don't do the reservation in non-hypervisor mode. This avoids unnecessary
CMA reservation when booting with limited memory configs like
On 29.09.14 13:48, Paolo Bonzini wrote:
Il 29/09/2014 10:28, Alexander Graf ha scritto:
On 29.09.14 10:02, Aneesh Kumar K.V wrote:
We use cma reserved area for creating guest hash page table.
Don't do the reservation in non-hypervisor mode. This avoids unnecessary
CMA reservation when
Il 29/09/2014 13:57, Alexander Graf ha scritto:
On 29.09.14 13:48, Paolo Bonzini wrote:
Il 29/09/2014 10:28, Alexander Graf ha scritto:
On 29.09.14 10:02, Aneesh Kumar K.V wrote:
We use cma reserved area for creating guest hash page table.
Don't do the reservation in non-hypervisor
From: Mihai Caraman mihai.cara...@freescale.com
Make ONE_REG generic for server and embedded architectures by moving
kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf
From: Mihai Caraman mihai.cara...@freescale.com
Now that AltiVec and hardware thread support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10
From: Mihai Caraman mihai.cara...@freescale.com
Powerpc timer implementation is a copycat version of s390. Now that they removed
the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this
optimization.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by:
From: Mihai Caraman mihai.cara...@freescale.com
Increase FPU laziness by loading the guest state into the unit before entering
the guest instead of doing it on each vcpu schedule. Without this improvement
an interrupt may claim floating point corrupting guest state.
Signed-off-by: Mihai Caraman
From: Paul Mackerras pau...@samba.org
Since the guest can read the machine's PVR (Processor Version Register)
directly and see the real value, we should disallow userspace from
setting any value for the guest's PVR other than the real host value.
Therefore this makes kvm_arch_vcpu_set_sregs_hv()
From: Michael Neuling mi...@neuling.org
Add 'r' to register name r2 in kvmppc_hv_enter.
Also update comment at the top of kvmppc_hv_enter to indicate that R2/TOC is
non-volatile.
Signed-off-by: Michael Neuling mi...@neuling.org
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by:
From: Mihai Caraman mihai.cara...@freescale.com
Add AltiVec support in KVM for Book3e. FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Book3e specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2
From: Paul Mackerras pau...@au1.ibm.com
Occasional failures have been seen with split-core mode and migration
where the message KVM: couldn't grab cpu appears. This increases
the length of time that we wait from 1ms to 10ms, which seems to
work around the issue.
Signed-off-by: Paul Mackerras
From: Mihai Caraman mihai.cara...@freescale.com
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and
From: Mihai Caraman mihai.cara...@freescale.com
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
From: Bharat Bhushan bharat.bhus...@freescale.com
This was missed in respective one_reg implementation patch.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/api.txt | 2 ++
1 file changed, 2 insertions(+)
The kvmppc_get_last_inst function recently received a facelift that allowed
us to pass an enum of the type of instruction we want to read into it rather
than an unreadable boolean.
Unfortunately, not all callers ended up passing the enum. This wasn't really
an issue as true and false happen to
From: Mihai Caraman mihai.cara...@freescale.com
Move ONE_REG AltiVec support to powerpc generic layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/uapi/asm/kvm.h | 5 +
arch/powerpc/kvm/book3s.c |
From: Bharat Bhushan bharat.bhus...@freescale.com
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always
From: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/booke.c| 6 ++
2 files changed, 7 insertions(+)
diff --git
From: Bharat Bhushan bharat.bhus...@freescale.com
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
From: Mihai Caraman mihai.cara...@freescale.com
Book3E specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which unit to support
exclusively. As
From: Bharat Bhushan bharat.bhus...@freescale.com
This patch changes the default behavior of MSRP_DEP, that is
guest is not allowed to change the MSR_DE, to guest can change
MSR_DE. When userspace is debugging guest then it override the
default behavior and set MSRP_DEP. This stops guest to
Hi Paolo,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit f51770ed465e6eb41da7fa16fd92eb67069600cf:
kvm: Make init_rmode_identity_map() return 0 on success. (2014-09-17 13:10:12
+0200)
are available in the git repository at:
From: Mihai Caraman mihai.cara...@freescale.com
We currently decide at compile-time which of the SPE or AltiVec units to
support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and
CONFIG_PPC_E500MC and remove shared defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
From: Madhavan Srinivasan ma...@linux.vnet.ibm.com
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com
From: Bharat Bhushan bharat.bhus...@freescale.com
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is
Il 24/09/2014 22:43, Alexander Graf ha scritto:
Hi Paolo,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit f51770ed465e6eb41da7fa16fd92eb67069600cf:
kvm: Make init_rmode_identity_map() return 0 on success. (2014-09-17
13:10:12 +0200)
On Fri, 2014-09-12 at 09:12 -0500, Purcareata Bogdan-B43198 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 11, 2014 9:19 PM
To: Purcareata Bogdan-B43198
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org
Subject: Re: [PATCH] KVM: PPC: Convert openpic
This patch enables running intensive I/O workloads, e.g. netperf, in a guest
deployed on a RT host. No change for !RT kernels.
The openpic spinlock becomes a sleeping mutex on a RT system. This no longer
guarantees that EPR is atomic with exception delivery. The guest VCPU thread
fails due to a
On Thu, 2014-09-11 at 15:25 -0400, Bogdan Purcareata wrote:
This patch enables running intensive I/O workloads, e.g. netperf, in a guest
deployed on a RT host. No change for !RT kernels.
The openpic spinlock becomes a sleeping mutex on a RT system. This no longer
guarantees that EPR is
On 09.09.14 19:07, Madhavan Srinivasan wrote:
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com
The kvmppc_get_last_inst function recently received a facelift that allowed
us to pass an enum of the type of instruction we want to read into it rather
than an unreadable boolean.
Unfortunately, not all callers ended up passing the enum. This wasn't really
an issue as true and false happen to
On Monday 08 September 2014 06:35 PM, Alexander Graf wrote:
On 07.09.14 18:31, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check
On Monday 08 September 2014 06:39 PM, Alexander Graf wrote:
On 07.09.14 18:31, Madhavan Srinivasan wrote:
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com
---
Patch is only compile tested. Will really help
This patchset adds ppc64 server side support for software breakpoint
and extends the use of illegal instruction as software
breakpoint across ppc platform.
Patch 1, adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to
hypervisor via
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software
On 09.09.14 19:07, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host
On 09.09.14 19:07, Madhavan Srinivasan wrote:
This patchset adds ppc64 server side support for software breakpoint
and extends the use of illegal instruction as software
breakpoint across ppc platform.
Patch 1, adds kernel side support for software breakpoint.
Design is that, by using an
On 07.09.14 18:31, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host
On 07.09.14 18:31, Madhavan Srinivasan wrote:
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com
This patchset adds ppc64 server side support for software breakpoint
and extends the use of illegal instruction as software
breakpoint across ppc platform.
Patch 1, adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to
hypervisor via
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software
This patch extends the use of illegal instruction as software
breakpoint instruction across the ppc platform. Patch extends
booke program interrupt code to support software breakpoint.
Signed-off-by: Madhavan Srinivasan ma...@linux.vnet.ibm.com
---
Patch is only compile tested. Will really help
Is There specific any reason not to copy extra handler IOVR 35 for e500?
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -527,7 +527,7 @@ static struct kvmppc_ops kvm_ops_e500 = {
static int __init kvmppc_e500_init(void)
{
int r, i;
- unsigned long ivor[3];
+
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Amit Tomar
Sent: Thursday, September 04, 2014 8:34 PM
To: ag...@suse.de; kvm-ppc@vger.kernel.org; Caraman Mihai Claudiu-B02008;
pbonz...@redhat.com
Subject: Patch - support
Il 02/09/2014 18:13, Laurent Dufour ha scritto:
fc95ca7284bc54953165cba76c3228bd2cdb9591 introduces a memset in
kvmppc_alloc_hpt since the general CMA doesn't clear the memory it
allocates.
However, the size argument passed to memset is computed from a signed value
and its signed bit is
On 01.09.14 11:01, Mihai Caraman wrote:
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional
This series of patches is based on Alex Graf's kvm-ppc-queue branch.
It contains 3 small patches from the tree that we are shipping on
POWER8 machines: a fix for an error that we see very occasionally,
and two minor improvements. Please apply for 3.18.
Paul.
---
Since the guest can read the machine's PVR (Processor Version Register)
directly and see the real value, we should disallow userspace from
setting any value for the guest's PVR other than the real host value.
Therefore this makes kvm_arch_vcpu_set_sregs_hv() check the supplied
PVR value and return
This provides basic support for the KVM_REG_PPC_ARCH_COMPAT register
in PR KVM. At present the value is sanity-checked when set, but
doesn't actually affect anything yet.
Implementing this makes it possible to use a qemu command-line
argument such as -cpu host,compat=power7 on a POWER8 machine,
From: Paul Mackerras pau...@au1.ibm.com
Occasional failures have been seen with split-core mode and migration
where the message KVM: couldn't grab cpu appears. This increases
the length of time that we wait from 1ms to 10ms, which seems to
work around the issue.
Signed-off-by: Paul Mackerras
fc95ca7284bc54953165cba76c3228bd2cdb9591 introduces a memset in
kvmppc_alloc_hpt since the general CMA doesn't clear the memory it
allocates.
However, the size argument passed to memset is computed from a signed value
and its signed bit is extended by the cast the compiler is doing. This lead
to
I abandon this patch, I will send a v2 with a minor fix for 85xx.
Mike
-Original Message-
From: Mihai Caraman [mailto:mihai.cara...@freescale.com]
Sent: Friday, August 29, 2014 8:04 PM
To: kvm-ppc@vger.kernel.org
Cc: k...@vger.kernel.org; Caraman Mihai Claudiu-B02008
Subject:
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional instruction, the Linux kernel uses per core
Now that AltiVec and hardware thread support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- new patch
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c
On Thu, Aug 28, 2014 at 03:13:03PM +0200, Radim Krčmář wrote:
In the beggining was on_each_cpu(), which required an unused argument to
kvm_arch_ops.hardware_{en,dis}able, but this was soon forgotten.
Remove unnecessary arguments that stem from this.
Signed-off-by: Radim Krčmář
We currently decide at compile-time which of the SPE or AltiVec units to
support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and
CONFIG_PPC_E500MC and remove shared defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/kvm_asm.h | 20
Powerpc timer implementation is a copycat version of s390. Now that they removed
the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this
optimization.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com
---
On 01.09.14 16:19, Mihai Caraman wrote:
Powerpc timer implementation is a copycat version of s390. Now that they
removed
the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this
optimization.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by:
On 01.09.14 12:17, Mihai Caraman wrote:
We currently decide at compile-time which of the SPE or AltiVec units to
support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and
CONFIG_PPC_E500MC and remove shared defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
On 28.08.14 15:13, Radim Krčmář wrote:
The first patch answers a demand for inline arch functions.
(There is a lot of constant functions that could be inlined as well.)
Second patch digs a bit into the history of KVM and removes a useless
argument that seemed suspicious when preparing the
Now that AltiVec and hardware threading support are in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index
On 13.08.14 11:09, Bharat Bhushan wrote:
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using
In the beggining was on_each_cpu(), which required an unused argument to
kvm_arch_ops.hardware_{en,dis}able, but this was soon forgotten.
Remove unnecessary arguments that stem from this.
Signed-off-by: Radim Krčmář rkrc...@redhat.com
---
arch/arm/include/asm/kvm_host.h | 2 +-
Using static inline is going to save few bytes and cycles.
For example on powerpc, the difference is 700 B after stripping.
(5 kB before)
This patch also deals with two overlooked empty functions:
kvm_arch_flush_shadow was not removed from arch/mips/kvm/mips.c
2df72e9bc KVM: split
The first patch answers a demand for inline arch functions.
(There is a lot of constant functions that could be inlined as well.)
Second patch digs a bit into the history of KVM and removes a useless
argument that seemed suspicious when preparing the first patch.
Radim Krčmář (2):
KVM: static
On 20.08.14 15:09, Mihai Caraman wrote:
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and
On 19.08.14 06:59, Michael Neuling wrote:
Add 'r' to register name r2 in kvmppc_hv_enter.
Also update comment at the top of kvmppc_hv_enter to indicate that R2/TOC is
non-volatile.
Signed-off-by: Michael Neuling mi...@neuling.org
Signed-off-by: Paul Mackerras pau...@samba.org
Thanks,
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